Mise à jour du 13 mars 2010

Research Pages

Reversible Computer

Titres

Copy of the Micropower Project
by Dr. Robert Glück et al.

Reversible Computing by
Pr. Alexis De Vos

The Reversible and Quantum
Computing Research Group
University of FLORIDA

Bibliography
by Stéphane BURIGNAT

Video Encoding

Reversible Circuits Synthesis

Reversible Logic Design

Bibliography on Reversible Logic Design - Table

JabRef References output

Author / Editor / Organization	Title	Year	Journal / Proceedings / Book	BibTeX type	DOI/URL
Arabzadeh, M.; Saeedi, M. & Zamani, M.S.	Rule-based optimization of reversible circuits [Abstract] [BibTeX]	2010	Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific , pp. 849 -854	inproceedings	DOI
Abstract: Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed. To evaluate the proposed approach, the best-reported synthesized circuits and the results of a recent synthesis algorithm which uses both negative and positive controls are used. Our experiments reveal the potential of the proposed approach in optimizing synthesized circuits.
BibTeX: @inproceedings{2010_Arabzadeh, author = {Arabzadeh, Mona and Saeedi, Mehdi and Zamani, Morteza Saheb}, title = {Rule-based optimization of reversible circuits}, journal = {Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific}, year = {2010}, pages = {849 -854}, doi = {http://dx.doi.org/10.1109/ASPDAC.2010.5419685} }
Arabzadeh, M.; Saeedi, M. & Zamani, M.S.	Rule-based optimization of reversible circuits [Abstract] [BibTeX]	2010	Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific , pp. 849 -854	inproceedings	DOI
Abstract: Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed. To evaluate the proposed approach, the best-reported synthesized circuits and the results of a recent synthesis algorithm which uses both negative and positive controls are used. Our experiments reveal the potential of the proposed approach in optimizing synthesized circuits.
BibTeX: @inproceedings{2010_Arabzadeha, author = {Arabzadeh, Mona and Saeedi, Mehdi and Zamani, Morteza Saheb}, title = {Rule-based optimization of reversible circuits}, journal = {Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific}, year = {2010}, pages = {849 -854}, doi = {http://dx.doi.org/10.1109/ASPDAC.2010.5419684} }
Das, K. & De, D.	Novel approach to design a testable conservative logic gate for QCA implementation [Abstract] [BibTeX]	2010	Advance Computing Conference (IACC), 2010 IEEE 2nd International , pp. 82 -87	inproceedings	DOI
Abstract: In the Low power Nanocomputing era, Reversible and Conservative logic gate design is emerging as an important area of research. In this paper, we present a Novel approach to design conservative logic gate (CLG) using 3 #x00D7;3 tile nanostructure, as reversible logic design research gets amplitude. On the other hand study of 3 #x00D7;3 tile make fruitful result as it have diverse application, mentioned in this paper. It is a Novel nanostructure that is applied here to implement CLG. The basic principle of CLG is Parity preserving in both input as well as output. Here we applied 3 #x00D7;3 orthogonal MV to implement the logic and Cross wire is implemented with the help of 3 #x00D7;3 Baseline tile. The main advantage of this design we achieve that the numbers of Layer required only one. It also been demonstrated that the proposed design offers less numbers of QCA cell as well as less area and less clocking zones then the existing counterparts. We also analyzed the logic synthesis using our proposed gate. Here, we also found an effective and promising result and excels all existing counterparts. We demonstrate the testability of proposed CLG by means of behavioral approach of both inputs and outputs.
BibTeX: @inproceedings{2010_Das, author = {Das, Kunal and De, Debashis}, title = {Novel approach to design a testable conservative logic gate for QCA implementation}, journal = {Advance Computing Conference (IACC), 2010 IEEE 2nd International}, year = {2010}, pages = {82 -87}, doi = {http://dx.doi.org/10.1109/IADCC.2010.5423034} }
Hashmi, I. & Babu, H.	An Efficient Design of a Reversible Barrel Shifter [Abstract] [BibTeX]	2010	VLSI Design, 2010. VLSID '10. 23rd International Conference on , pp. 93 -98	inproceedings	DOI
Abstract: The key objective of today's circuit design is to increase the performance without the proportional increase in power consumption. In this regard, reversible logic has become an immensely promising technology in the field of low power computing and designing. On the other hand, data shifting and rotating are required in many operations such as arithmetic and logical operations, address decoding and indexing etc. In this consequence, barrel shifters, which can shift and rotate multiple bits in a single cycle, have become a common design choice for high speed applications. For this reason, this paper presents an efficient design of a reversible barrel shifter. It has also been shown that the new circuit outperforms the previously proposed one in terms of number of gates, number of garbage outputs, delay and quantum cost.
BibTeX: @inproceedings{2010_Hashmi, author = {Hashmi, I. and Babu, H.M.H.}, title = {An Efficient Design of a Reversible Barrel Shifter}, journal = {VLSI Design, 2010. VLSID '10. 23rd International Conference on}, year = {2010}, pages = {93 -98}, doi = {http://dx.doi.org/10.1109/VLSI.Design.2010.35} }
Thapliyal, H. & Ranganathan, N.	Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs [Abstract] [BibTeX]	2010	VLSI Design, 2010. VLSID '10. 23rd International Conference on , pp. 235 -240	inproceedings	DOI
Abstract: Reversible logic has extensive applications in emerging nanotechnologies, such as quantum computing, optical computing, ultra low power VLSI and quantum dot cellular automata. In the existing literature, designs of reversible sequential circuits are presented that are optimized for the number of reversible gates and the garbage outputs. The optimization of the number of reversible gates is not sufficient since each reversible gate is of different computational complexity, and thus will have a different quantum cost and delay. While the computational complexity of a reversible gate can be measured by its quantum cost, the delay of a reversible gate is another parameter that can be optimized during the design of a reversible sequential circuit. In this work, we present novel designs of reversible latches that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of reversible latches presented in this work are the D Latch, JK latch, T latch and SR latch.
BibTeX: @inproceedings{2010_Thapliyal, author = {Thapliyal, Himanshu and Ranganathan, Nagarajan}, title = {Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs}, journal = {VLSI Design, 2010. VLSID '10. 23rd International Conference on}, year = {2010}, pages = {235 -240}, doi = {http://dx.doi.org/10.1109/VLSI.Design.2010.74} }
Thapliyal, H. & Ranganathan, N.	Reversible Logic-Based Concurrently Testable Latches for Molecular QCA [Abstract] [BibTeX]	2010	Nanotechnology, IEEE Transactions on Vol. 9 (1) , pp. 62 -69	article	DOI
Abstract: Nanotechnologies, including molecular quantum dot cellular automata (QCA), are susceptible to high error rates. In this paper, we present the design of concurrently testable latches (D latch, T latch, JK latch, and SR latch), which are based on reversible conservative logic for molecular QCA. Conservative reversible circuits are a specific type of reversible circuits, in which there would be an equal number of 1's in the outputs as there would be on the inputs, in addition to one-to-one mapping. Thus, conservative logic is parity-preserving, i.e., the parity of the input vectors is equal to that of the output vectors. We analyzed the fault patterns in the conservative reversible Fredkin gate due to a single missing/additional cell defect in molecular QCA. We found that if there is a fault in the molecular QCA implementation of Fredkin gate, there is a parity mismatch between the inputs and the outputs, otherwise the inputs parity is the same as outputs parity. Any permanent or transient fault in molecular QCA can be concurrently detected if implemented with the conservative Fredkin gate. The design of QCA layouts and the verification of the latch designs using the QCADesigner and the HDLQ tool are presented.
BibTeX: @article{2010_Thapliyala, author = {Thapliyal, H. and Ranganathan, N.}, title = {Reversible Logic-Based Concurrently Testable Latches for Molecular QCA}, journal = {Nanotechnology, IEEE Transactions on}, year = {2010}, volume = {9}, number = {1}, pages = {62 -69}, doi = {http://dx.doi.org/10.1109/TNANO.2009.2025038} }
Feinstein, D. & Thornton, M.	On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering [Abstract] [BibTeX]	2009	Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on , pp. 132 -138	inproceedings	DOI
Abstract: This paper proposes a framework that improves reversible logic synthesis by employing a dynamically determined variable order for quantum multiple-valued decision diagrams (QMDD). We demonstrate our approach through augmentation of the Miller-Maslov-Dueck (MMD) algorithm that processes the complete function specification in lexicographical order with our technique. We represent and minimize the complete specification with the QMDD and then synthesize the function specification based on the minimized variable order. The framework produces significantly smaller reversible circuits in many cases. Experimental results also show the effectiveness of using the QMDD size as a measure of the complexity of MVL and binary reversible circuits.
BibTeX: @inproceedings{2009_Feinstein, author = {Feinstein, D.Y. and Thornton, M.A.}, title = {On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering}, journal = {Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on}, year = {2009}, pages = {132 -138}, doi = {http://dx.doi.org/10.1109/ISMVL.2009.31} }
Grosse, D.; Wille, R.; Dueck, G. & Drechsler, R.	Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques [Abstract] [BibTeX]	2009	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 28 (5) , pp. 703 -715	article	DOI
Abstract: Synthesis of reversible logic has become a very important research area in recent years. Applications can be found in the domain of low-power design, optical computing, and quantum computing. In the past, several approaches have been introduced that synthesize reversible networks with respect to a given function. Most of these methods only approximate a minimal network representation. In this paper, exact algorithms for the synthesis of multiple-control Toffoli networks are presented, i.e., algorithms that guarantee to find a network with the minimal number of gates. Our iterative algorithms formulate the synthesis problem as a sequence of decision problems. The decision problems are encoded as Boolean satisfiability (SAT) or SAT modulo theory (SMT) instances, respectively. As soon as one of these instances becomes satisfiable, a Toffoli network representation for the given function has been found. We show that choosing the encoding for synthesis is crucial for the resulting runtimes. Furthermore, we discuss the principal limits of the SAT and SMT approaches. To overcome these limits, we propose a method using problem-specific knowledge during synthesis. In addition, better embeddings to make irreversible functions reversible are considered. For the resulting synthesis problems, an improvement is presented that reduces the overall runtime by automatically setting the constant inputs to their optimal values. Experimental results on a large set of benchmarks demonstrate the differences between three exact synthesis algorithms. In addition, a comparison with the best-known heuristic results is provided. In summary, the results show that, for some benchmarks, the heuristic approaches have already found the minimal network, while for other benchmarks, significantly smaller networks exist.
BibTeX: @article{2009_Grosse, author = {Grosse, D. and Wille, R. and Dueck, G.W. and Drechsler, R.}, title = {Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2009}, volume = {28}, number = {5}, pages = {703 -715}, doi = {http://dx.doi.org/10.1109/TCAD.2009.2017215} }
Guan, Z.; Bao, Z. & Jing, W.	The Cascade of the Reversible Gate Network-Based the Dynamic Binary Spanning Tree [Abstract] [BibTeX]	2009	Computer Science and Engineering, 2009. WCSE '09. Second International Workshop on Vol. 1 , pp. 403 -407	inproceedings	DOI
Abstract: This paper proposed the reversible logic gate network cascade method-based the reversible logic gate the Dynamic binary spanning tree, which can generate single reversible network or the batching continuous sequence numbers reversible network. The search time and search space are reduced by the corresponding relationship between the variable system numbers and reversible network output vectors, we can locate quickly the corresponding sequence numbers of the reversible network output vectors and judge previously whether the output vectors have been appeared. Compared with examples of the benchmark, the number of control-bit and the number of the reversible logic gates have been improved to some degree.
BibTeX: @inproceedings{2009_Guan, author = {Zhijin Guan and Zhihua Bao and Weiping Jing}, title = {The Cascade of the Reversible Gate Network-Based the Dynamic Binary Spanning Tree}, journal = {Computer Science and Engineering, 2009. WCSE '09. Second International Workshop on}, year = {2009}, volume = {1}, pages = {403 -407}, doi = {http://dx.doi.org/10.1109/WCSE.2009.697} }
Guan, Z.; Zhang, Y. & Lu, Y.	Reversible Logic Gate Cascade Network Based on Series Connection [Abstract] [BibTeX]	2009	Computational Intelligence and Security, 2009. CIS '09. International Conference on Vol. 1 , pp. 468 -472	inproceedings	DOI
Abstract: This paper analyzes and proves that the relationship between the output results of the homotypic Toffoli gate, which is series cascade and the number of the gates. In order to guarantee the convergence of the process of the series cascade, we gave the counting results of the series cascade network for Toffoli gates, and proved that the number of the bit vectors with Hamming weight H(w)Â¿ n-1 is equal to the bit number of bit vectors plus 1, and obtained the conclusion that there are (n+1)! kinds of transformation for Toffoli gate series cascade network. Simultaneously we provide the series cascade network algorithm of the Toffoli gates. The reversible network cascade system designed by the above algorithm verified the validity of this algorithm.
BibTeX: @inproceedings{2009_Guana, author = {Zhijin Guan and Yiqing Zhang and Yanming Lu}, title = {Reversible Logic Gate Cascade Network Based on Series Connection}, journal = {Computational Intelligence and Security, 2009. CIS '09. International Conference on}, year = {2009}, volume = {1}, pages = {468 -472}, doi = {http://dx.doi.org/10.1109/CIS.2009.19} }
Hasan, M.; Islam, A. & Chowdhury, A.	Design and analysis of online testability of reversible sequential circuits [Abstract] [BibTeX]	2009	Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on , pp. 180 -185	inproceedings	DOI
Abstract: Reversible logic plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design and nanotechnology-based system. In this paper, we have proposed the online testability of reversible sequential circuits, which is first ever proposed in literature. On the way to propose the online testability of reversible sequential circuits, we have proposed an improved rail-check circuit that significantly improves the performance of the overall circuit in terms of gate cost and garbage cost parameters. We have also used our improved and efficient rail-check circuit to realize the testability of different benchmark circuits.
BibTeX: @inproceedings{2009_Hasan, author = {Hasan, M. and Islam, A.K.M.T. and Chowdhury, A.R.}, title = {Design and analysis of online testability of reversible sequential circuits}, journal = {Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on}, year = {2009}, pages = {180 -185}, doi = {http://dx.doi.org/10.1109/ICCIT.2009.5407143} }
Islam, M.; Rahman, M.; Begum, Z. & Hafiz, M.	Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders [Abstract] [BibTeX]	2009	Advances in Computational Tools for Engineering Applications, 2009. ACTEA '09. International Conference on , pp. 396 -401	inproceedings	DOI
Abstract: Irreversible logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed 16-bit high speed reversible adder will include IG gates for the realization of its basic building block. The IG gate is universal in the sense that it can be used to synthesize any arbitrary Boolean-functions. The IG gate is parity preserving, that is, the parity of the inputs matches the parity of the outputs. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Therefore, the proposed high speed adders will have the inherent opportunity of detecting errors in its output side. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
BibTeX: @inproceedings{2009_Islam, author = {Islam, M.S. and Rahman, M.M. and Begum, Z. and Hafiz, M.Z.}, title = {Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders}, journal = {Advances in Computational Tools for Engineering Applications, 2009. ACTEA '09. International Conference on}, year = {2009}, pages = {396 -401}, doi = {http://dx.doi.org/10.1109/ACTEA.2009.5227871} }
Islam, S.; Rahman, M.; Begum, Z.; Hafiz, Z. & Al Mahmud, A.	Synthesis of Fault Tolerant Reversible Logic Circuits [Abstract] [BibTeX]	2009	Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on , pp. 1 -4	inproceedings	DOI
Abstract: Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 universal reversible logic gate, IG. It is a parity preserving reversible logic gate, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Finally, it is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
BibTeX: @inproceedings{2009_Islama, author = {Islam, S. and Rahman, M.M. and Begum, Z. and Hafiz, Z. and Al Mahmud, A.}, title = {Synthesis of Fault Tolerant Reversible Logic Circuits}, journal = {Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on}, year = {2009}, pages = {1 -4}, doi = {http://dx.doi.org/10.1109/CAS-ICTD.2009.4960883} }
Khan, M.	Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits [Abstract] [BibTeX]	2009	Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on , pp. 343 -348	inproceedings	DOI
Abstract: Quaternary reversible logic is very suitable for encoded realization of binary reversible logic functions by grouping two bits together into quaternary digits. Quaternary multiplexer and demultiplexer circuits are very important building blocks of quaternary digital systems. In this paper, we show reversible realizations of 4x1 multiplexer and 1x4 demultiplexer circuits on the top of liquid ion-trap realizable 1x1 and Muthukrishnan-Stroud gates. Then we show scalable architectures for design of mx1 multiplexer and 1xm demultiplexer circuits using 4x1 multiplexers and 1x4 demultiplexers, respectively, where m les 4n and n is the number of selection inputs. The proposed realizations of reversible multiplexer and demultiplexer circuits are more efficient than the earlier realizations in terms of number of primitive gates and number of ancilla inputs required.
BibTeX: @inproceedings{2009_Khan, author = {Khan, M.H.A.}, title = {Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits}, journal = {Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on}, year = {2009}, pages = {343 -348}, doi = {http://dx.doi.org/10.1109/ISMVL.2009.26} }
Nayeem, N.; Hossain, M.; Jamal, L. & Babu, H.	Efficient Design of Shift Registers Using Reversible Logic [Abstract] [BibTeX]	2009	2009 International Conference on Signal Processing Systems , pp. 474 -478	inproceedings	DOI
Abstract: Reversible shift registers are required to construct reversible memory circuits. This paper presents novel designs of reversible shift registers such as serial-in serial-out (SISO), serial-in parallel-out (SIPO), parallel-in serial-out (PISO), parallel-in parallel-out (PIPO) and universal shift registers. In order to show the efficiency, lower bounds of the proposed designs are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement shift registers (except SISO). Appropriate theorems and lemmas are presented to clarify the proposed designs. The contribution of this paper will engender a new thread of research in the field of reversible sequential circuits.
BibTeX: @inproceedings{2009_Nayeem, author = {Nayeem, N.M. and Hossain, M.A. and Jamal, L. and Babu, H.M.H.}, title = {Efficient Design of Shift Registers Using Reversible Logic}, journal = {2009 International Conference on Signal Processing Systems}, year = {2009}, pages = {474 -478}, doi = {http://dx.doi.org/10.1109/ICSPS.2009.166} }
Nayeem, N.; Hossain, A.; Haque, M.; Jamal, L. & Babu, H.	Novel reversible division hardware [Abstract] [BibTeX]	2009	Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on , pp. 1134 -1138	inproceedings	DOI
Abstract: This paper presents a novel design of sequential division circuit using reversible logic, which is a promising research area nowadays. The proposed hardware has its application in the design of reversible arithmetic logic unit. In order to show the efficiency, lower bounds of the proposed design are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement division hardware. As the works in the field of reversible logic has only started to bloom, the contribution of this paper will engender a new thread of research in the field of reversible division circuit.
BibTeX: @inproceedings{2009_Nayeema, author = {Nayeem, N.M. and Hossain, A. and Haque, M. and Jamal, L. and Babu, H.}, title = {Novel reversible division hardware}, journal = {Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on}, year = {2009}, pages = {1134 -1138}, doi = {http://dx.doi.org/10.1109/MWSCAS.2009.5235968} }
Nower, N. & Chowdhury, A.	Realization of systolic array using ternary reversible gates [Abstract] [BibTeX]	2009	Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on , pp. 192 -196	inproceedings	DOI
Abstract: Multi valued logic synthesis is a very promising and affluent research area at present because of allowing designers to build much more efficient computers than the existing classical ones. Ternary logic synthesis research has got impetus in the recent years. Many existing literature are mainly perceptive to the realization of efficient ternary reversible processors. This research is based on the design of a reversible systolic array, which is one of the best examples of parallel processing, using micro level ternary Toffoli gate. General architecture of the ternary reversible systolic array multiplier is shown along with example. Lower bound for the garbage outputs produced in the proposed design and the quantum cost of the entire circuit is calculated here to prove the compactness of the design.
BibTeX: @inproceedings{2009_Nower, author = {Nower, N. and Chowdhury, A.R.}, title = {Realization of systolic array using ternary reversible gates}, journal = {Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on}, year = {2009}, pages = {192 -196}, doi = {http://dx.doi.org/10.1109/ICCIT.2009.5407141} }
Parise, G.; Hesla, E. & Rifaat, R.	Architecture Impact on Integrity of Electrical Installations: Cut hash x00026;Tie Rule, Ring Configuration, Floating Node [Abstract] [BibTeX]	2009	Industry Applications, IEEE Transactions on Vol. 45 (5) , pp. 1903 -1909	article	DOI
Abstract: An electrical distribution architecture has a vital impact on the performance of an installed system throughout its lifecycle. The architecture of an installation involves the configuration, the choice of power sources (utility and alternate power source), the definition of the different distribution levels, and the choice of equipment. Previous papers have introduced a language program for analyzing and transcribing the instructions of the safety procedures for each working zone and of the integrity procedures for each source node versus the loss of service continuity (the Parise program). Each node presents a kit of instructions as a logic gene, describing a complete and reversible evolution of the component switching means from an opening status to a closing one. This paper deals with the architecture of a power system and the combination of procedures in the operation on a nodes system. It will show the impact of the architecture on the comprehensive procedures for a complex system. To enhance the integrity of power system analysis and operation, the design could adopt the cut amp;tie rule, introducing ring configuration and floating nodes. The suggested advanced approach assists in the elaboration of the procedures for switching from one set or configuration of a power system to another and will help the training of operators in defining the instructions to be used in the development and the operating of each power system.
BibTeX: @article{2009_Parise, author = {Parise, G. and Hesla, E. and Rifaat, R.M.}, title = {Architecture Impact on Integrity of Electrical Installations: Cut hash x00026;Tie Rule, Ring Configuration, Floating Node}, journal = {Industry Applications, IEEE Transactions on}, year = {2009}, volume = {45}, number = {5}, pages = {1903 -1909}, doi = {http://dx.doi.org/10.1109/TIA.2009.2027181} }
Sasanian, Z.; Saeedi, M.; Sedighi, M. & Zamani, M.	A cycle-based synthesis algorithm for reversible logic [Abstract] [BibTeX]	2009	Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific , pp. 745 -750	inproceedings	DOI
Abstract: Several algorithms have been proposed for the synthesis of reversible circuits. In this paper, a cycle-based synthesis algorithm for reversible logic, based on the NCT library, has been proposed. In other words, direct implementation of a single 3-cycle, a pair of 3-cycles and a pair of 2-cycles have been explored and used to propose an efficient Toffoli-based synthesis algorithm for reversible circuits. The synthesis algorithm decomposes a given large cycle into a set of single 3-cycles, pairs of 3-cycles and pair of 2-cycles and synthesizes the resulted cycles directly. Our experimental results show that the proposed synthesis algorithm can outperform the available 2-cycle-based approach about 34% on average. In addition, several discussions for the generalization of the proposed method to the 2m-cycles are given.
BibTeX: @inproceedings{2009_Sasanian, author = {Sasanian, Z. and Saeedi, M. and Sedighi, M. and Zamani, M.S.}, title = {A cycle-based synthesis algorithm for reversible logic}, journal = {Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific}, year = {2009}, pages = {745 -750}, doi = {http://dx.doi.org/10.1109/ASPDAC.2009.4796569} }
Tabei, K. & Yamada, T.	On generating test sets for reversible circuits [Abstract] [BibTeX]	2009	Computer Engineering Systems, 2009. ICCES 2009. International Conference on , pp. 94 -99	inproceedings	DOI
Abstract: Reversible circuits are quite attractive because of the possibility of nearly energy-free computation. During designing and constructing a reversible circuit, it is important to test the circuit and detect faults in the circuit. However, very few algorithms are known to generate a complete test set for a given reversible circuit. In this paper, first of all, it is NP-hard to generate a minimum complete test set for stuck-at faults even when a given reversible circuit is restricted to use only three kinds of simple reversible gates, that is NOT, 1-CNOT, and Toffoli gates. Therefore, it seems to be quite difficult, or even impossible, to generate minimum complete test sets for practical reversible circuits. Next, the paper presents a randomized algorithm to generate a complete test set for stuck-at faults in a given reversible circuit. As far as the authors know, the proposed algorithm is the first one to guarantee that the expected time complexity is polynomial and that the size of the obtained test size is bounded. Finally, the effectiveness of the proposed algorithm is shown by experiments.
BibTeX: @inproceedings{2009_Tabei, author = {Tabei, K. and Yamada, T.}, title = {On generating test sets for reversible circuits}, journal = {Computer Engineering Systems, 2009. ICCES 2009. International Conference on}, year = {2009}, pages = {94 -99}, doi = {http://dx.doi.org/10.1109/ICCES.2009.5383305} }
Takahashi, K. & Hirayama, T.	Reversible logic synthesis from positive Davio trees of logic functions [Abstract] [BibTeX]	2009	TENCON 2009 - 2009 IEEE Region 10 Conference , pp. 1 -4	inproceedings	DOI
Abstract: Considering the Landauer's principle, a reversible logic circuit is said to be energy conservation compared with conventional digital circuit. In this paper, we propose and implement a reversible logic synthesis algorithm utilizing the positive Davio trees of logic functions. We synthesize a reversible logic circuit by replacing the each node with reversible logic gates, and connecting them. Moreover, by sharing the nodes being able to share, we purpose the synthesis of circuits of the fewer gates, and the fewer garbage lines.
BibTeX: @inproceedings{2009_Takahashi, author = {Takahashi, K. and Hirayama, T.}, title = {Reversible logic synthesis from positive Davio trees of logic functions}, journal = {TENCON 2009 - 2009 IEEE Region 10 Conference}, year = {2009}, pages = {1 -4}, doi = {http://dx.doi.org/10.1109/TENCON.2009.5395805} }
Thapliyal, H. & Ranganathan, N.	Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate [Abstract] [BibTeX]	2009	Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on , pp. 1815 -1818	inproceedings	DOI
Abstract: Reversible logic is attracting the researchers attention for fault susceptible nanotechnologies including molecular QCA. In this paper, we propose concurrently testable FPGA design for molecular QCA using conservative reversible Fredkin gate. Fredkin gate is conservative reversible in nature, in which there would be an equal number of 1s in the outputs as there would be on the inputs, in addition to one-to-one mapping. Fault patterns in Fredkin gate are analyzed using HDLQ tool due to a single missing/additional cell defect in molecular QCA. Exhaustive simulation shows that if there is a fault in molecular QCA implementation of Fredkin gate, there is a parity mismatch between the inputs and the outputs; otherwise the inputs parity is same as outputs parity. Thus, any permanent and transient fault in molecular QCA that results in parity mismatch can be concurrently detected. The logic block and the routing fabric (both are programmable) are the two key components of an FPGA. Thus, we have shown the Fredkin gate based concurrently testable designs of the configurable logic block (CLB) and the routing switch of a molecular QCA-based FPGA. Analysis of power dissipation in the proposed FPGA is also shown.
BibTeX: @inproceedings{2009_Thapliyal, author = {Thapliyal, H. and Ranganathan, N.}, title = {Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate}, journal = {Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on}, year = {2009}, pages = {1815 -1818}, doi = {http://dx.doi.org/10.1109/ISCAS.2009.5118130} }
Thapliyal, H. & Ranganathan, N.	Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate [Abstract] [BibTeX]	2009	VLSI, 2009. ISVLSI '09. IEEE Computer Society Annual Symposium on , pp. 229 -234	inproceedings	DOI
Abstract: Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.
BibTeX: @inproceedings{2009_Thapliyala, author = {Thapliyal, H. and Ranganathan, N.}, title = {Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate}, journal = {VLSI, 2009. ISVLSI '09. IEEE Computer Society Annual Symposium on}, year = {2009}, pages = {229 -234}, doi = {http://dx.doi.org/10.1109/ISVLSI.2009.49} }
Vasudevan, D.; Goudarzi, M.; Popovici, E. & Schellekens, M.	A Reversible MIPS multi-cycle control FSM design [Abstract] [BibTeX]	2009	Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on , pp. 336 -342	inproceedings	DOI
Abstract: Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced in this paper. Three FSMs namely original, reverse and reversible FSM of the MIPS control circuit is designed, synthesized and simulated. Synthesis and simulation results are provided for the three implementations. The overhead for designing the reversible FSM are log2(N)rceil conflict pins and one direction pin along with extra logic for inserting them.
BibTeX: @inproceedings{2009_Vasudevan, author = {Vasudevan, D. and Goudarzi, M. and Popovici, E. and Schellekens, M.}, title = {A Reversible MIPS multi-cycle control FSM design}, journal = {Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on}, year = {2009}, pages = {336 -342}, doi = {http://dx.doi.org/10.1109/ASQED.2009.5206242} }
Wille, R. & Drechsler, R.	BDD-based synthesis of reversible logic for large functions [Abstract] [BibTeX]	2009	Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE , pp. 270 -275	inproceedings
Abstract: Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a binary decision diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.
BibTeX: @inproceedings{2009_Wille, author = {Wille, R. and Drechsler, R.}, title = {BDD-based synthesis of reversible logic for large functions}, journal = {Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE}, year = {2009}, pages = {270 -275} }
Wille, R.; Grosse, D.; Miller, D. & Drechsler, R.	Equivalence Checking of Reversible Circuits [Abstract] [BibTeX]	2009	Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on , pp. 324 -330	inproceedings	DOI
Abstract: Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits' primary inputs and outputs must be in pure logic states but the circuits may include elementary quantum gates in addition to reversible logic gates. The specification can include don't-cares arising from constant inputs, garbage outputs, and total or partial don't-cares in the underlying target function. The paper explores well-known techniques from irreversible equivalence checking and how they can be applied in the domain of reversible circuits. Two approaches are considered. The first employs decision diagram techniques and the second uses Boolean satisfiability. Experimental results show that for both methods, circuits with up to 27,000 gates, as well as adders with more than 100 inputs and outputs, are handled in under three minutes with reasonable memory requirements.
BibTeX: @inproceedings{2009_Willea, author = {Wille, R. and Grosse, D. and Miller, D.M. and Drechsler, R.}, title = {Equivalence Checking of Reversible Circuits}, journal = {Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on}, year = {2009}, pages = {324 -330}, doi = {http://dx.doi.org/10.1109/ISMVL.2009.19} }
Wille, R.; Grosse, D.; Dueck, G. & Drechsler, R.	Reversible Logic Synthesis with Output Permutation [Abstract] [BibTeX]	2009	VLSI Design, 2009 22nd International Conference on , pp. 189 -194	inproceedings	DOI
Abstract: Synthesis of reversible logic has become a very important research area. In recent years several algorithms--heuristic as well as exact ones--have been introduced in this area. Typically, they use the specification of a reversible function in terms of a truth table as input. Here, the position of the outputs are fixed. However, in general it is irrelevant, how the respective outputs are ordered. Thus, a synthesis methodology is proposed that determines for a given reversible function an equivalent circuit realization modulo output permutation. More precisely, the result of the synthesis process is a circuit realization whose output functions have been permuted in comparison to the original specification and the respective permutation vector. We show that this synthesis methodology may lead to significant smaller realizations. We apply Synthesis with Output Permutation (SWOP) to both, an exact and a heuristic synthesis algorithm. As our experiments show using the new synthesis paradigm leads to multiple control Toffoli networks that are smaller than the currently best known realizations.
BibTeX: @inproceedings{2009_Willeb, author = {Wille, R. and Grosse, D. and Dueck, G.W. and Drechsler, R.}, title = {Reversible Logic Synthesis with Output Permutation}, journal = {VLSI Design, 2009 22nd International Conference on}, year = {2009}, pages = {189 -194}, doi = {http://dx.doi.org/10.1109/VLSI.Design.2009.40} }
Wille, R.; Grosse, D.; Frehse, S.; Dueck, G. & Drechsler, R.	Debugging of Toffoli networks [Abstract] [BibTeX]	2009	Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09. , pp. 1284 -1289	inproceedings
Abstract: Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible logic synthesis, testing, and verification have been investigated, debugging of reversible circuits has not yet been considered. The goal of debugging is to determine gates of an erroneous circuit that explain the observed incorrect behavior. In this paper we propose the first approach for automatic debugging of reversible Toffoli networks. Our method uses a formulation for the debugging problem based on Boolean satisfiability. We show the differences to classical (irreversible) debugging and present theoretical results. These are used to speed-up the debugging approach as well as to improve the resulting quality. Our method is able to find and to correct single errors automatically.
BibTeX: @inproceedings{2009_Willec, author = {Wille, R. and Grosse, D. and Frehse, S. and Dueck, G.W. and Drechsler, R.}, title = {Debugging of Toffoli networks}, journal = {Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09.}, year = {2009}, pages = {1284 -1289} }
Zhang, M.; Zhao, S. & Wang, X.	Automatic synthesis of reversible logic circuit based on genetic algorithm [Abstract] [BibTeX]	2009	Intelligent Computing and Intelligent Systems, 2009. ICIS 2009. IEEE International Conference on Vol. 3 , pp. 542 -546	inproceedings	DOI
Abstract: The reversible logic circuits (RLC) are a sort of novel circuits which can avoid the information loss and energy dissipation by implementing the reversible logic operations. RLC prohibit the feedback and don't have the fan-out, so the synthesis methods of RLC are very different from the existing irreversible logic circuits. In this paper, evolutionary design techniques are applied to the synthesis of RLC, and then an automatic synthesis approach of RLC based on genetic algorithm is proposed. Firstly, some appropriate reversible logic gates are chosen as the building-blocks, and a computational array model is built for the synthesis of RLC. According to the array model, the synthesis problems are modeled as the constrained multi-objective optimization problems which are converted into their single-objective equivalents by the weighted sum of objective functions. Then, the single-objective equivalents are solved by a specialized genetic algorithm. The experimental results verify the capability of automatic synthesis of the proposed approach, and show that the proposed approach is feasible and effective.
BibTeX: @inproceedings{2009_Zhang, author = {Mingming Zhang and Shuguang Zhao and Xu Wang}, title = {Automatic synthesis of reversible logic circuit based on genetic algorithm}, journal = {Intelligent Computing and Intelligent Systems, 2009. ICIS 2009. IEEE International Conference on}, year = {2009}, volume = {3}, pages = {542 -546}, doi = {http://dx.doi.org/10.1109/ICICISYS.2009.5358132} }
Zheng, Y. & Huang, C.	A novel Toffoli network synthesis algorithm for reversible logic [Abstract] [BibTeX]	2009	Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific , pp. 739 -744	inproceedings	DOI
Abstract: Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input output correspondence which makes the logic synthesis for reversible functions differs greatly from traditional Boolean functions. Exact synthesis methods can provide optimal solutions in terms of the total number of reversible gates in the synthesis results. Unfortunately, they may suffer from long computation time, due to the fact that the search space is likely to grow exponentially as the circuit size increases. Therefore, in this paper, we propose an efficient synthesis heuristic which provides high quality synthesis results of Toffoli network in more reasonable computation time. We use a weighted, directed graph for reversible function representation and complexity measurement. The proposed algorithm maximally decreases function complexity during synthesis steps. It has the ability to climb out of local minimums and guarantees algorithm convergence. The experimental results show that our algorithm can achieve optimal or very close to optimal solutions with computation time several orders of magnitude less than the exact methods. Compared with other heuristics, our method demonstrates superior performance in terms of reversible gate count as well as computation time.
BibTeX: @inproceedings{2009_Zheng, author = {Yexin Zheng and Chao Huang}, title = {A novel Toffoli network synthesis algorithm for reversible logic}, journal = {Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific}, year = {2009}, pages = {739 -744}, doi = {http://dx.doi.org/10.1109/ASPDAC.2009.4796568} }
Zhu, W.; Guan, Z. & Hang, Y.	Reversible Logic Synthesis of Networks of Positive/Negative Control Gates [Abstract] [BibTeX]	2009	Natural Computation, 2009. ICNC '09. Fifth International Conference on Vol. 6 , pp. 538 -542	inproceedings	DOI
Abstract: The research in reversible logic has been attracted in recent years. It has applications in quantum computing, low-power CMOS design and nanotechnology. Many methods on how to cascade a reversible network have been proposed. And all these networks are composed of Toffoli/Fredkin gates. In this paper, we present a method that synthesizes a network with family of Positive/Negative Control (PNC) gates. Through introducing some examples for 3Ã3 reversible functions, and comparing with the network which is composed of Toffoli gates, the results show that introducing the PNC gates can produce an improvement for the number of gates in the reversible network, and have an advantage in reducing the cost of network.
BibTeX: @inproceedings{2009_Zhu, author = {Wenying Zhu and Zhijin Guan and Yueqing Hang}, title = {Reversible Logic Synthesis of Networks of Positive/Negative Control Gates}, journal = {Natural Computation, 2009. ICNC '09. Fifth International Conference on}, year = {2009}, volume = {6}, pages = {538 -542}, doi = {http://dx.doi.org/10.1109/ICNC.2009.186} }
Ardestani, E.; Zamani, M. & Sedighi, M.	A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits [Abstract] [BibTeX]	2008	Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on , pp. 803 -806	inproceedings	DOI
Abstract: In this paper, a simple and fast algorithm for the synthesis of reversible circuits is presented. This algorithm considers the synthesis process as a kind of sorting problem, generating a reversible circuit composed of CNOT-based gates. We prove that the proposed algorithm converges for any given specification. The empirical results of realizing examples discussed in the literature are reported. The results show that the algorithm leads to a near optimum solution for all 3*3 specifications and very good results for other larger specifications in much fewer steps compared to the search based and other previous algorithms.
BibTeX: @inproceedings{2008_Ardestani, author = {Ardestani, E.K. and Zamani, M.S. and Sedighi, M.}, title = {A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits}, journal = {Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on}, year = {2008}, pages = {803 -806}, doi = {http://dx.doi.org/10.1109/DSD.2008.95} }
Biswas, A.; Hasan, M.; Hasan, M.; Chowdhury, A. & Babu, H.	A Novel Approach to Design BCD Adder and Carry Skip BCD Adder [Abstract] [BibTeX]	2008	VLSI Design, 2008. VLSID 2008. 21st International Conference on , pp. 566 -571	inproceedings	DOI
Abstract: Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage output and delay.
BibTeX: @inproceedings{2008_Biswas, author = {Biswas, A.K. and Hasan, M.M. and Hasan, M. and Chowdhury, A.R. and Babu, H.M.H.}, title = {A Novel Approach to Design BCD Adder and Carry Skip BCD Adder}, journal = {VLSI Design, 2008. VLSID 2008. 21st International Conference on}, year = {2008}, pages = {566 -571}, doi = {http://dx.doi.org/10.1109/VLSI.2008.37} }
Chou, Y.-H.; Tsai, I.-M. & Kuo, S.-Y.	Quantum Boolean Circuits are 1-Testable [Abstract] [BibTeX]	2008	Nanotechnology, IEEE Transactions on Vol. 7 (4) , pp. 484 -492	article	DOI
Abstract: Recently, a systematic procedure was proposed to derive a minimum input quantum circuit for any given classical logic with the generalized quantum Toffoli gate, which is universal in Boolean logic. Since quantum Boolean circuits are reversible, we can apply this property to build quantum iterative logic array (QILA). QILA can be easily tested in constant time (C-testable) if stuck-at fault model is assumed. In this paper, we use Hadamard and general controlled-controlled not gates to make QILA 1-testable. That is, for any quantum Boolean circuit, the number of test patterns is independent of both the size of the array and the length of the inputs.
BibTeX: @article{2008_Chou, author = {Yao-Hsin Chou and I-Ming Tsai and Sy-Yen Kuo}, title = {Quantum Boolean Circuits are 1-Testable}, journal = {Nanotechnology, IEEE Transactions on}, year = {2008}, volume = {7}, number = {4}, pages = {484 -492}, doi = {http://dx.doi.org/10.1109/TNANO.2008.926369} }
Feinstein, D.; Thornton, M. & Miller, D.	Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits [Abstract] [BibTeX]	2008	Design, Automation and Test in Europe, 2008. DATE '08 , pp. 1378 -1381	inproceedings	DOI
Abstract: This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.
BibTeX: @inproceedings{2008_Feinstein, author = {Feinstein, D.Y. and Thornton, M.A. and Miller, D.M.}, title = {Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits}, journal = {Design, Automation and Test in Europe, 2008. DATE '08}, year = {2008}, pages = {1378 -1381}, doi = {http://dx.doi.org/10.1109/DATE.2008.4484932} }
Grosse, D.; Wille, R.; Dueck, G. & Drechsler, R.	Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares [Abstract] [BibTeX]	2008	Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on , pp. 214 -219	inproceedings	DOI
Abstract: Compact realizations of reversible logic functions are of interest in the design of quantum computers. In this paper we present an exact synthesis algorithm, based on Boolean satisfiability (SAT), that finds the minimal elementary quantum gate realization for a given reversible function. Since these gates work in terms of qubits, a multi-valued encoding is proposed. Don't care conditions appear naturally in many reversible functions. Constant inputs are often required when a function is embedded into a reversible one. The proposed algorithm takes full advantage of don't care conditions and automatically sets the constant inputs to their optimal values. The effectiveness of the algorithm is shown on a set of benchmark functions.
BibTeX: @inproceedings{2008_Grosse, author = {Grosse, D. and Wille, R. and Dueck, G.W. and Drechsler, R.}, title = {Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares}, journal = {Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on}, year = {2008}, pages = {214 -219}, doi = {http://dx.doi.org/10.1109/ISMVL.2008.42} }
Hasan, M.	Low-cost realization of toffoli gate for the low-cost synthesis of quantum ternary logic functions [Abstract] [BibTeX]	2008	Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on , pp. 259 -263	inproceedings	DOI
Abstract: Reversible quantum computer system is one of the best choices for future computer systems. Multiple-valued logic especially ternary logic is a good candidate for the realization of reversible quantum computer. An efficient logic synthesis mechanism is essential for the low-cost realization. Toffoli gate is an important gate for quantum logic synthesis. It is the basic element for the Galois Field Sum of Product (GFSOP) expression based logic synthesis mechanism. So, for low-cost realization of any ternary logic function, a low-cost implementation of Toffoli gate is very necessary. This paper shows a low-cost, practically realizable, and efficient realization of 3-qutrit ternary Toffoli gate by using ion-trap realizable Muthukrishnan-Stroud gate. This realization is more efficient and less costly than other realizations.
BibTeX: @inproceedings{2008_Hasan, author = {Hasan, M.M.}, title = {Low-cost realization of toffoli gate for the low-cost synthesis of quantum ternary logic functions}, journal = {Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on}, year = {2008}, pages = {259 -263}, doi = {http://dx.doi.org/10.1109/ICCITECHN.2008.4803024} }
Ibrahim, M.; Chowdhury, A. & Babu, H.	Minimization of CTS of k-CNOT Circuits for SSF and MSF Model [Abstract] [BibTeX]	2008	Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on , pp. 290 -298	inproceedings	DOI
Abstract: In this paper, we consider the problem of testing reversible circuits for a particular fault model: Stuck-at Fault Model. We propose a design-for-test construction technique for k-CNOT circuit having k ges 1 and only 2 test vector (i.e. minimal) suffice as their complete test set. We have also shown the way to exploit our method for the case of 0-CNOT circuits. Finally we provide some experimental results for the proposed method and compare it with existing method to show how the proposed one outperforms the existing one both in terms of number of test vectors of complete test set and number of gates need to be replaced in the design-for-test.
BibTeX: @inproceedings{2008_Ibrahim, author = {Ibrahim, M. and Chowdhury, A.R. and Babu, H.}, title = {Minimization of CTS of k-CNOT Circuits for SSF and MSF Model}, journal = {Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on}, year = {2008}, pages = {290 -298}, doi = {http://dx.doi.org/10.1109/DFT.2008.38} }
Ibrahim, M.; Chowdhury, A. & Babu, H.	On the minimization of complete test set of reversible k-CNOT circuits for Stuck-at Fault model [Abstract] [BibTeX]	2008	Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on , pp. 7 -12	inproceedings	DOI
Abstract: In this paper, we propose an algorithm that produces the complete test set (CTS) of a reversible circuit for Single stuck-at fault (SSF) and multiple-stuck-at fault (MSF) models. Our algorithm works only for an important subclass of reversible circuits - the circuits consisting of k-CNOT gates (k ges 2) though, any n-wire circuit having 0-CNOT or 1-CNOT gates can be converted to a (n + 2) wire circuit having only k-CNOT gates with k ges 2 with some additional hardware cost. Generated complete test set is not necessarily optimal, but minimizing the size of the complete test set is our key concern. Finally we provide some experimental results for the proposed method and compare it with existing methods to show how it outperforms almost all of the existing algorithms in terms of number of elements of CTS but is outperformed by some of the existing ones in terms of hardware cost.
BibTeX: @inproceedings{2008_Ibrahima, author = {Ibrahim, M. and Chowdhury, A.R. and Babu, H.}, title = {On the minimization of complete test set of reversible k-CNOT circuits for Stuck-at Fault model}, journal = {Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on}, year = {2008}, pages = {7 -12}, doi = {http://dx.doi.org/10.1109/ICCITECHN.2008.4803009} }
Khan, M.; Biswas, A.; Chowdhury, S.; Tanzid, M.; Mohsin, K.; Hasan, M. & Khan, A.	Quantum realization of some quaternary circuits [Abstract] [BibTeX]	2008	TENCON 2008 - 2008 IEEE Region 10 Conference , pp. 1 -5	inproceedings	DOI
Abstract: We present the design of quaternary quantum version of reversible circuits such as Toffoli gate, modified Fredkin gate, mux, demux, encoder-decoder using linear ion realizable quaternary Muthukrishnan-Stroud gates. Our realization of quaternary Toffoli gate is more efficient than the previous realization and other quaternary circuits are realized for the time in literature.
BibTeX: @inproceedings{2008_Khan, author = {Khan, M.M.M. and Biswas, A.K. and Chowdhury, S. and Tanzid, M. and Mohsin, K.M. and Hasan, M. and Khan, A.I.}, title = {Quantum realization of some quaternary circuits}, journal = {TENCON 2008 - 2008 IEEE Region 10 Conference}, year = {2008}, pages = {1 -5}, doi = {http://dx.doi.org/10.1109/TENCON.2008.4766486} }
Khanoma, R.; Kamalb, T. & Khana, M.	Genetic Algorithm based synthesis of ternary Reversible/Quantum circuit [Abstract] [BibTeX]	2008	Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on , pp. 270 -275	inproceedings	DOI
Abstract: Reversible/quantum circuits are believed to be one of the future computer technologies. In this paper, a genetic algorithm (GA) based synthesis of ternary reversible/quantum circuits using Muthukrishnan-Stroud gates is presented. The circuit generated by GA may contain redundant gates. We have used post GA reduction to eliminate these redundant gates. We have experimented with ternary half-adder circuit. The proposed GA converges for many combinations of crossover and mutation.
BibTeX: @inproceedings{2008_Khanoma, author = {Khanoma, R. and Kamalb, T. and Khana, M.}, title = {Genetic Algorithm based synthesis of ternary Reversible/Quantum circuit}, journal = {Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on}, year = {2008}, pages = {270 -275}, doi = {http://dx.doi.org/10.1109/ICCITECHN.2008.4803043} }
Mathew, J.; Rahaman, H.; Jose, B. & Pradhan, D.	Design of Reversible Finite Field Arithmetic Circuits with Error Detection [Abstract] [BibTeX]	2008	VLSI Design, 2008. VLSID 2008. 21st International Conference on , pp. 453 -459	inproceedings	DOI
Abstract: Motivated by the potential of reversible computing, we present a systematic method for the designing reversible arithmetic circuits for finite field or Galois fields of form GF(2m). It is shown that an adder over GF(2m) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits. To tackle the problem of errors in computation, we also extend the circuit with error detection feature. Gate count and technology oriented cost metrics are used for evaluation. The expression for the upper bound for gate size is also derived for special primitive polynomials. Our technique, when compared with existing CAD tool gives the same gate size and quantum cost.
BibTeX: @inproceedings{2008_Mathew, author = {Mathew, J. and Rahaman, H. and Jose, B.R. and Pradhan, D.K.}, title = {Design of Reversible Finite Field Arithmetic Circuits with Error Detection}, journal = {VLSI Design, 2008. VLSID 2008. 21st International Conference on}, year = {2008}, pages = {453 -459}, doi = {http://dx.doi.org/10.1109/VLSI.2008.96} }
Mathew, J.; Singh, J.; Taleb, A. & Pradhan, D.	Fault Tolerant Reversible Finite Field Arithmetic Circuits [Abstract] [BibTeX]	2008	On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International , pp. 188 -189	inproceedings	DOI
Abstract: In this paper, we present a systematic method for the designing fault tolerant reversible arithmetic circuits for finite field or Galois fields of the form GF(2m). To tackle the problem of errors in computation, we propose error detection and correction using multiple parity prediction technique based on low density parity check (LDPC) code. For error detection and correction, we need additional garbage outputs. Our technique, when compared with traditional fault tolerant approach gives better implementation cost.
BibTeX: @inproceedings{2008_Mathewa, author = {Mathew, J. and Singh, J. and Taleb, A.A. and Pradhan, D.K.}, title = {Fault Tolerant Reversible Finite Field Arithmetic Circuits}, journal = {On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International}, year = {2008}, pages = {188 -189}, doi = {http://dx.doi.org/10.1109/IOLTS.2008.35} }
Mohammadi, M.; Eshghi, M. & Haghparast, M.	On design of multiple-valued sequential reversible circuits for nanotechnology based systems [Abstract] [BibTeX]	2008	TENCON 2008 - 2008 IEEE Region 10 Conference , pp. 1 -6	inproceedings	DOI
Abstract: Multiple-valued reversible logic is an emerging area in reversible and quantum logic circuit synthesis. Multiple-valued reversible logic circuits can potentially reduce the width of the reversible or quantum circuit which is a limitation in current quantum technology. In this paper we propose a method to synthesize the multiple-valued reversible sequential circuits. Implementations for ternary D and T flip flops and edge triggered D flip flop are proposed. Synthesis of generalized fanout circuit and generalized r-valued T flip flop are also presented.
BibTeX: @inproceedings{2008_Mohammadi, author = {Mohammadi, M. and Eshghi, M. and Haghparast, M.}, title = {On design of multiple-valued sequential reversible circuits for nanotechnology based systems}, journal = {TENCON 2008 - 2008 IEEE Region 10 Conference}, year = {2008}, pages = {1 -6}, doi = {http://dx.doi.org/10.1109/TENCON.2008.4766407} }
Mohammadi, M. & Eshghi, M.	Behavioral description of quantum V and V+ gates to design quantum logic circuits [Abstract] [BibTeX]	2008	Systems, Signals and Devices, 2008. IEEE SSD 2008. 5th International Multi-Conference on , pp. 1 -5	inproceedings	DOI
Abstract: Quantum gates which are represented by unitary matrices have potentials to implement reversible logic circuits. V and V+ gates are two well known quantum gates which are used to synthesize the reversible logic circuits. In this paper we have used behavioral description of these gates, instead of unitary matrix description, to synthesize reversible logic circuits. By this method, V and V+ gates are shown in the truth table form. Results show that bigger circuits with more number of gates can be synthesized using proposed method. Some benchmarks of reversible logic circuits are also optimized and compared to other works.
BibTeX: @inproceedings{2008_Mohammadia, author = {Mohammadi, M. and Eshghi, M.}, title = {Behavioral description of quantum V and V+ gates to design quantum logic circuits}, journal = {Systems, Signals and Devices, 2008. IEEE SSD 2008. 5th International Multi-Conference on}, year = {2008}, pages = {1 -5}, doi = {http://dx.doi.org/10.1109/SSD.2008.4632850} }
Naderpour, F. & Vafaei, A.	Reversible multipliers: Decreasing the depth of the circuit [Abstract] [BibTeX]	2008	Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on , pp. 306 -310	inproceedings	DOI
Abstract: There are many arithmetic operations which are performed, on a computer arithmetic unit, through the use of multipliers (e.g., exponential and trigonometric functions). Consequently, optimized multipliers are on demand while designing an arithmetic unit. On the other hand, given the advent of quantum computer and reversible logic, design and implementation of digital circuits in this logic has gained popularity. In reversible circuit design, decreasing three parameters is of interest: quantum cost, depth of the circuit and the number of garbage outputs. In this paper, we propose a novel reversible multiplier with the aim of decreasing the depth of the circuit while neither scarifying any extra quantum cost nor garbage outputs. The partial products, as is the case for prior works, are generated in parallel using Peres gates and thereafter a reversible multi-operand adder consisting of reversible full-adders and half-adders produces the final product.
BibTeX: @inproceedings{2008_Naderpour, author = {Naderpour, F. and Vafaei, A.}, title = {Reversible multipliers: Decreasing the depth of the circuit}, journal = {Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on}, year = {2008}, pages = {306 -310}, doi = {http://dx.doi.org/10.1109/ICECE.2008.4769222} }
Naderpour, F. & Vafaei, A.	The Design of Reversible BCD Digit Adders: Decreasing the Depth of Circuit [Abstract] [BibTeX]	2008	Communications and Information Technologies, 2008. ISCIT 2008. International Symposium on , pp. 310 -314	inproceedings	DOI
Abstract: Reversible circuits, nowadays, have found grounds in many applications such as low power CMOS design and quantum computing. In reversible circuit design, decreasing three parameters is of interest: quantum cost, depth of the circuit and the number of garbage outputs. On the other hand, recently, decimal computer arithmetic, for the sake of its preciseness, gains popularity. Given that the BCD digit adder is the basic unit in decimal arithmetic, in this paper we propose a new reversible design for this unit with the aim of minimizing the depth of the circuit. Furthermore, we show that the proposed designing method can be applied to any other reversible circuit for reaching the minimum depth.
BibTeX: @inproceedings{2008_Naderpoura, author = {Naderpour, F. and Vafaei, A.}, title = {The Design of Reversible BCD Digit Adders: Decreasing the Depth of Circuit}, journal = {Communications and Information Technologies, 2008. ISCIT 2008. International Symposium on}, year = {2008}, pages = {310 -314}, doi = {http://dx.doi.org/10.1109/ISCIT.2008.4700204} }
Ogunti, E.; Frank, M. & Foo, S.	Design of a low power binary counter using bistable storage element [Abstract] [BibTeX]	2008	Electronic Design, 2008. ICED 2008. International Conference on , pp. 1 -5	inproceedings	DOI
Abstract: An architecture for a O(1)-loss irreversible n-bit counter is presented in this paper. It is presented as an initial stepping stone application that is suitable for clarifying the potential energy-efficiency advantages of reversible computing. It is based on using fairly standard, irreversible, semi-static CMOS logic. Care is taken to ensure that energy is not dissipated at subsequent counter bits, except those that are actually changing values on a given cycle. The design utilizes two-phase non-overlapping clocks, phi0 and phi1 with fast rise and fall times. For high system level energy-efficiency, the clocks were generated resonantly using the rotary clock scheme. XOR gates serve as phase detectors with AND gates helping to maintain parity checking. Transmission gates ensure a semi-static logic since the logic levels are restored only during the high portion of the clock period. We compared the power dissipation of an 8-bit counter designed using this logic to a standard 8-bit binary counter design using flip-flops in the 50 nm process and recorded a power advantage of about 60%. A prototype will be sent to MOSIS for fabrication to confirm energy advantage of this design after testing.
BibTeX: @inproceedings{2008_Ogunti, author = {Ogunti, E. and Frank, M. and Foo, S.}, title = {Design of a low power binary counter using bistable storage element}, journal = {Electronic Design, 2008. ICED 2008. International Conference on}, year = {2008}, pages = {1 -5}, doi = {http://dx.doi.org/10.1109/ICED.2008.4786672} }
Parise, G.; Hesla, E. & Rifaat, R.	Architecture impact on integrity of electrical installations: Cut hash x00026;tie rule, ring configuration, floating node [Abstract] [BibTeX]	2008	Industrial and Commercial Power Systems Technical Conference, 2008. ICPS 2008. IEEE/IAS , pp. 1 -7	inproceedings	DOI
Abstract: The electrical distribution architecture has a vital impact on performance of the installed system throughout its lifecycle. The architecture of an installation involves the configuration, the choice of power sources (utility and alternate power source) the definition of different distribution levels and the choice of equipment. Previous papers have introduced a language-program for analyzing and transcribing the instructions of safety procedures for each working zone WZ and of integrity procedures for each sources node versus the loss of service continuity (Parise's program). Each node presents a kit of instructions as a logic gene describing a complete and reversible evolution of the component switching means from a opening status to a closing one. This paper deals with the architecture of a power system and the combination of procedures in the operation on a nodes system. It will show the impact of the architecture on the comprehensive procedures for a complex system. To enhance the integrity of power system analysis and operation, the design could adopt the cut and tie rule, introducing ring configuration and floating nodes. The suggested advanced approach assists in the elaboration of the procedures for switching from one set or configuration of a power system to another and will help the training of operators in defining the instructions to be used in the development and the operating of each power system.
BibTeX: @inproceedings{2008_Parise, author = {Parise, G. and Hesla, E. and Rifaat, R.M.}, title = {Architecture impact on integrity of electrical installations: Cut hash x00026;tie rule, ring configuration, floating node}, journal = {Industrial and Commercial Power Systems Technical Conference, 2008. ICPS 2008. IEEE/IAS}, year = {2008}, pages = {1 -7}, doi = {http://dx.doi.org/10.1109/ICPS.2008.4606299} }
Rahaman, H.; Kole, D.; Das, D. & Bhattacharya, B.	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set [Abstract] [BibTeX]	2008	VLSI Design, 2008. VLSID 2008. 21st International Conference on , pp. 163 -168	inproceedings	DOI
Abstract: Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Newer technologies like ion trapping or nuclear magnetic resonance are required to emulate quantum gates. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely, single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. In this paper, it is shown that in an (n times n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate yields an easily testable design, which admits a universal test set of size (n +1) that detects all SMGFs, RGFs, and PMGFs in the circuit.
BibTeX: @inproceedings{2008_Rahaman, author = {Rahaman, H. and Kole, D.K. and Das, D.K. and Bhattacharya, B.B.}, title = {On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set}, journal = {VLSI Design, 2008. VLSID 2008. 21st International Conference on}, year = {2008}, pages = {163 -168}, doi = {http://dx.doi.org/10.1109/VLSI.2008.106} }
Sarkar, P. & Chakrabarti, S.	Universal test set for bridging fault detection in reversible circuit [Abstract] [BibTeX]	2008	Design and Test Workshop, 2008. IDT 2008. 3rd International , pp. 51 -56	inproceedings	DOI
Abstract: Detection of bridging faults plays a significant role in a reversible circuit. The single and multiple inputs bridging faults model of a reversible circuit is considered here. The paper proposes that only n (number of inputs) number of universal test vectors are sufficient for detection of all single and multiple input bridging faults and all input stuck-at faults of any n-input and n-output reversible circuit. A polynomial time algorithm is proposed for generating the universal test vectors for detecting of all single and multiple input bridging faults of the reversible circuit. The results on reversible benchmark circuit show that the number of universal test vectors are significantly reduced compared to the earlier works of reversible circuit and classical circuit.
BibTeX: @inproceedings{2008_Sarkar, author = {Sarkar, P. and Chakrabarti, S.}, title = {Universal test set for bridging fault detection in reversible circuit}, journal = {Design and Test Workshop, 2008. IDT 2008. 3rd International}, year = {2008}, pages = {51 -56}, doi = {http://dx.doi.org/10.1109/IDT.2008.4802464} }
Song, T.; Wang, S. & Wang, X.	The design of reversible gate and reversible sequential circuit based on DNA computing [Abstract] [BibTeX]	2008	Intelligent System and Knowledge Engineering, 2008. ISKE 2008. 3rd International Conference on Vol. 1 , pp. 114 -118	inproceedings	DOI
Abstract: Recently, the parallel computing power and ability of storing the information in nano scale have made the use of DNA molecules in a perfect computing paradigm. And the reversible logic has been taken as a significant paradigm in low power computing and it plays an important role in the synthesis of circuits for quantum computing. In this article, the reversible logic is proposed to be simulated by using DNA molecules and bio-chemistry operations: the input and the output of a reversible gate or a reversible sequential circuit are both DNA sequences, and the computing progresses correspond to the bio-chemistry operations. By sticking system and enzyme system, two kinds of DNA reversible gate are simulated, which are both called as the DNA Fredkin gate. Then the reversible sequential circuit can be simulated easily by using DNA Fredkin gates. And the DNA Fredkin gate can also be used for designing the optimal reversible sequential circuits. That must be a new computing model in both DNA computing and quantum computing.
BibTeX: @inproceedings{2008_Song, author = {Tao Song and Shudong Wang and Xun Wang}, title = {The design of reversible gate and reversible sequential circuit based on DNA computing}, journal = {Intelligent System and Knowledge Engineering, 2008. ISKE 2008. 3rd International Conference on}, year = {2008}, volume = {1}, pages = {114 -118}, doi = {http://dx.doi.org/10.1109/ISKE.2008.4730909} }
Thapliyal, H. & Ranganathan, N.	Testable Reversible Latches for Molecular QCA [Abstract] [BibTeX]	2008	Nanotechnology, 2008. NANO '08. 8th IEEE Conference on , pp. 699 -702	inproceedings	DOI
Abstract: Nanotechnologies, including molecular QCA, are susceptible to high error rates. In this paper, we present the design of testable reversible latches (D latch, T Latch, JK Latch, RS Latch), based on reversible conservative logic for molecular QCA. Conservative reversible circuits are a specific type of reversible circuits in which there would be an equal number of Is in the output as there would be on the input, in addition to one- to-one mapping. The proposed latches require only two test vectors, all Os and all Is, for detecting any unidirectional stuck-at faults. The design of QCA layouts and the verification of the latch designs performed using the QCA designer tool are presented.
BibTeX: @inproceedings{2008_Thapliyal, author = {Thapliyal, H. and Ranganathan, N.}, title = {Testable Reversible Latches for Molecular QCA}, journal = {Nanotechnology, 2008. NANO '08. 8th IEEE Conference on}, year = {2008}, pages = {699 -702}, doi = {http://dx.doi.org/10.1109/NANO.2008.211} }
Wille, R.; Grosse, D.; Teuber, L.; Dueck, G. & Drechsler, R.	RevLib: An Online Resource for Reversible Functions and Reversible Circuits [Abstract] [BibTeX]	2008	Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on , pp. 220 -225	inproceedings	DOI
Abstract: Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, results are often documented only in terms of gate counts or quantum costs, rather than presenting the specific circuit. In this paper RevLib (www.revlib.org) is introduced, an online resource for reversible functions and reversible circuits. RevLib provides a large database of functions with respective circuit realizations. RevLib is designed to ease the evaluation of new methods and facilitate the comparison of results. In addition, tools are introduced to support researchers in evaluating their algorithms and documenting their results.
BibTeX: @inproceedings{2008_Wille, author = {Wille, R. and Grosse, D. and Teuber, L. and Dueck, G.W. and Drechsler, R.}, title = {RevLib: An Online Resource for Reversible Functions and Reversible Circuits}, journal = {Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on}, year = {2008}, pages = {220 -225}, doi = {http://dx.doi.org/10.1109/ISMVL.2008.43} }
Wille, R.; Le, H.; Dueck, G. & Grosse, D.	Quantified Synthesis of Reversible Logic [Abstract] [BibTeX]	2008	Design, Automation and Test in Europe, 2008. DATE '08 , pp. 1015 -1020	inproceedings	DOI
Abstract: In the last years synthesis of reversible logic functions has emerged as an important research area. Other fields such as low-power design, optical computing and quantum computing benefit directly from achieved improvements. Recently, several approaches for exact synthesis of Toffoli networks have been proposed. They all use Boolean satisfiability to solve the underlying synthesis problem. In this paper a new exact synthesis approach based on Quantified Boolean Formula (QBF) satisfiability - a generalization of Boolean satisfiability - is presented. Besides the application of QBF solvers, we propose Binary Decision Diagrams to solve the quantified problem formulation. This allows to easily support different gate libraries during synthesis. In addition, all minimal networks are found in a single step and the best one with respect to quantum costs can be chosen. Experimental results confirm that the new technique is faster than the best previously known approach and leads to cheaper realizations in terms of quantum costs.
BibTeX: @inproceedings{2008_Willea, author = {Wille, R. and Le, H.M. and Dueck, G.W. and Grosse, D.}, title = {Quantified Synthesis of Reversible Logic}, journal = {Design, Automation and Test in Europe, 2008. DATE '08}, year = {2008}, pages = {1015 -1020}, doi = {http://dx.doi.org/10.1109/DATE.2008.4484814} }
ying Zhang, X.; li Wang, L. & gong Zhou, X.	Efficient RM conversion algorithm for large multiple output functions [Abstract] [BibTeX]	2008	Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on , pp. 2300 -2303	inproceedings	DOI
Abstract: RM (Reed-Muller) expansions have shown advantages compared with the traditional SOP (Sum-of-Products) forms in the areas of arithmetic logic, reversible logic synthesis and Boolean quantum circuit design. A new algorithm is presented for the conversion between SOP and RM forms of multiple output functions. This procedure is based on the cube set expressions and therefore independent on number of input variables. A verification method is also proposed to make sure the algorithm is correct. The experimental results show that the conversion algorithm is effective in terms of time for very large Boolean functions up to 199 inputs and 67 outputs.
BibTeX: @inproceedings{2008_Zhang, author = {Xiao-ying Zhang and Ling-li Wang and Xue-gong Zhou}, title = {Efficient RM conversion algorithm for large multiple output functions}, journal = {Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on}, year = {2008}, pages = {2300 -2303}, doi = {http://dx.doi.org/10.1109/ICSICT.2008.4735030} }
Bubna, M.; Goyal, N. & Sengupta, I.	A DFT methodology for detecting bridging faults in reversible logic circuits [Abstract] [BibTeX]	2007	TENCON 2007 - 2007 IEEE Region 10 Conference , pp. 1 -4	inproceedings	DOI
Abstract: Toffoli gate is a universal reversible logic gate by which any classical or quantum circuit can be synthesized. In this paper, we propose a design-for-test (DFT) method to make an arbitrary reversible logic circuit composed of n-bit Toffoli gates fully testable for single intra-level bridging faults and single stuck-at faults. We have considered testing of circuits composed of n-bit Toffoli gates. The proposed method requires exactly ([log2N] +3) test vectors, for 'N' input wires, which is independent of the number of gates in the circuit. We also give a universal test set for detecting these faults.
BibTeX: @inproceedings{2007_Bubna, author = {Bubna, M. and Goyal, N. and Sengupta, I.}, title = {A DFT methodology for detecting bridging faults in reversible logic circuits}, journal = {TENCON 2007 - 2007 IEEE Region 10 Conference}, year = {2007}, pages = {1 -4}, doi = {http://dx.doi.org/10.1109/TENCON.2007.4428915} }
Chuang, M.-L. & Wang, C.-Y.	Synthesis of Reversible Sequential Elements [Abstract] [BibTeX]	2007	Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific , pp. 420 -425	inproceedings	DOI
Abstract: To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as D latch, JK latch, and T latch. Based on these reversible latches, we also construct the designs of the corresponding flip-flops. Comparing with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs is considerably reduced.
BibTeX: @inproceedings{2007_Chuang, author = {Min-Lun Chuang and Chun-Yao Wang}, title = {Synthesis of Reversible Sequential Elements}, journal = {Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific}, year = {2007}, pages = {420 -425}, doi = {http://dx.doi.org/10.1109/ASPDAC.2007.358022} }
Gorgin, S. & Kaivani, A.	Reversible Barrel Shifters [Abstract] [BibTeX]	2007	Computer Systems and Applications, 2007. AICCSA '07. IEEE/ACS International Conference on , pp. 479 -483	inproceedings	DOI
Abstract: Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of quantum computer and reversible logic, design and implementation of all devices in this logic has received more attention. This paper proposes a reversible implementation of a barrel shifter, and also evaluation of its quantum cost is presented.
BibTeX: @inproceedings{2007_Gorgin, author = {Gorgin, S. and Kaivani, A.}, title = {Reversible Barrel Shifters}, journal = {Computer Systems and Applications, 2007. AICCSA '07. IEEE/ACS International Conference on}, year = {2007}, pages = {479 -483}, doi = {http://dx.doi.org/10.1109/AICCSA.2007.370925} }
Hu, J.; Ma, G. & Li, D.	Symbolic Optimization Method for Reversible Circuits [Abstract] [BibTeX]	2007	EUROCON, 2007. The International Conference on #34;Computer as a Tool #34; , pp. 521 -524	inproceedings	DOI
Abstract: Reversible circuits play an important role in low power design. In this paper, we propose an optimization method based on matrix model and symbolic algebra for reversible circuits considering multiple objectives, including area and delay. We have tested the proposed algorithm on a set of the reversible benchmark circuits. Compared with existing method, this heuristic reduces path delay by 12% on average. The improvements make optimization specially important for high performance and a large number of inputs and outputs designs.
BibTeX: @inproceedings{2007_Hu, author = {Jing Hu and GuangSheng Ma and Donghai Li}, title = {Symbolic Optimization Method for Reversible Circuits}, journal = {EUROCON, 2007. The International Conference on #34;Computer as a Tool #34;}, year = {2007}, pages = {521 -524}, doi = {http://dx.doi.org/10.1109/EURCON.2007.4400311} }
Huang, J.; Ma, X.; Metra, C. & Lombardi, F.	Testing Reversible One-Dimensional QCA Arrays for Multiple F [Abstract] [BibTeX]	2007	Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on , pp. 469 -477	inproceedings	DOI
Abstract: Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. C-testability of a ID array is investigated for multiple cell faults. It has been shown that fault masking is possible in the presence of multiple faults [9]. A technique for achieving C-testability of ID array is introduced by adding lines for controllability and observability. Rules for choosing lines for controllability and observability are proposed. Examples using the QCA reversible logic gates proposed in [9] are presented.
BibTeX: @inproceedings{2007_Huang, author = {Huang, J. and Ma, X. and Metra, C. and Lombardi, F.}, title = {Testing Reversible One-Dimensional QCA Arrays for Multiple F}, journal = {Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on}, year = {2007}, pages = {469 -477}, doi = {http://dx.doi.org/10.1109/DFT.2007.17} }
James, R.; Shahana, T.; Jacob, K. & Sasi, S.	A New Look at Reversible Logic Implementation of Decimal Adder [Abstract] [BibTeX]	2007	System-on-Chip, 2007 International Symposium on , pp. 1 -4	inproceedings	DOI
Abstract: Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The design reduces the number of gates and garbage outputs compared to the existing BCD adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay.
BibTeX: @inproceedings{2007_James, author = {James, R.K. and Shahana, T.K. and Jacob, K.P. and Sasi, S.}, title = {A New Look at Reversible Logic Implementation of Decimal Adder}, journal = {System-on-Chip, 2007 International Symposium on}, year = {2007}, pages = {1 -4}, doi = {http://dx.doi.org/10.1109/ISSOC.2007.4427442} }
James, R.; Shahana, T.; Jacob, K. & Sasi, S.	Quick Addition of Decimals Using Reversible Conservative Logic [Abstract] [BibTeX]	2007	Advanced Computing and Communications, 2007. ADCOM 2007. International Conference on , pp. 191 -196	inproceedings	DOI
Abstract: In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.
BibTeX: @inproceedings{2007_Jamesa, author = {James, R.K. and Shahana, T.K. and Jacob, K.P. and Sasi, S.}, title = {Quick Addition of Decimals Using Reversible Conservative Logic}, journal = {Advanced Computing and Communications, 2007. ADCOM 2007. International Conference on}, year = {2007}, pages = {191 -196}, doi = {http://dx.doi.org/10.1109/ADCOM.2007.94} }
James, R.; Shahana, T.; Jacob, K. & Sasi, S.	Fault tolerant error coding and detection using reversible gates [Abstract] [BibTeX]	2007	TENCON 2007 - 2007 IEEE Region 10 Conference , pp. 1 -4	inproceedings	DOI
Abstract: In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction - double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4times4 reversible gate called 'HCG' for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.
BibTeX: @inproceedings{2007_Jamesb, author = {James, R.K. and Shahana, T.K. and Jacob, K.P. and Sasi, S.}, title = {Fault tolerant error coding and detection using reversible gates}, journal = {TENCON 2007 - 2007 IEEE Region 10 Conference}, year = {2007}, pages = {1 -4}, doi = {http://dx.doi.org/10.1109/TENCON.2007.4428776} }
Li, W.; Chen, H. & Li, Z.	Application of Semi-Template in Reversible Logic Circuit [Abstract] [BibTeX]	2007	Computer Supported Cooperative Work in Design, 2007. CSCWD 2007. 11th International Conference on , pp. 332 -336	inproceedings	DOI
Abstract: To improve the technique of optimizing reversible logic circuit and reduce the cost of reversible logic circuit, the template technology is analyzed, finding that Maslov's templates are incomplete in that the control lines are incomplete. By introducing the library of template control lines concept, templates are reconstructed and named semi-template. The semi-templates do not realize the identity function, but more valid templates can be produced dynamically using template producing rule. And based on this method, an algorithm is provided to optimize reversible logic circuit. Experimental data show that this method is more efficient and has higher rate of matching success in optimizing reversible logic circuit.
BibTeX: @inproceedings{2007_Li, author = {Wenqian Li and Hanwu Chen and Zhiqiang Li}, title = {Application of Semi-Template in Reversible Logic Circuit}, journal = {Computer Supported Cooperative Work in Design, 2007. CSCWD 2007. 11th International Conference on}, year = {2007}, pages = {332 -336}, doi = {http://dx.doi.org/10.1109/CSCWD.2007.4281457} }
Maslov, D. & Miller, D.	Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits [Abstract] [BibTeX]	2007	Computers Digital Techniques, IET Vol. 1 (2) , pp. 98 -104	article	DOI
Abstract: A breadth-first search method for determining optimal three-qubit circuits composed of quantum NOT, CNOT, controlled-V and controlled-V + (NCV) gates is introduced. Results are presented for simple gate count and for technology-motivated cost metrics. The optimal NCV circuits are also compared with NCV circuits derived from optimal NOT, CNOT and Toffoli (NCT) gate circuits. This work provides basic results and motivation for continued study of the direct synthesis of NCV circuits, and establishes relations between function realizations in different circuit cost metrics
BibTeX: @article{2007_Maslov, author = {Maslov, D. and Miller, D.M.}, title = {Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits}, journal = {Computers Digital Techniques, IET}, year = {2007}, volume = {1}, number = {2}, pages = {98 -104}, doi = {http://dx.doi.org/10.1049/iet-cdt:20060070} }
Saeedi, M.; Sedighi, M. & Zamani, M.	A novel synthesis algorithm for reversible circuits [Abstract] [BibTeX]	2007	Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on , pp. 65 -68	inproceedings	DOI
Abstract: In this paper, a new non-search based synthesis algorithm for reversible circuits is proposed. Compared with the widely used search-based methods, our algorithm is guaranteed to produce a result and can lead to a solution with much fewer steps. To evaluate the proposed method, several circuits taken from the literature are used. The experimental results corroborate the expected findings.
BibTeX: @inproceedings{2007_Saeedi, author = {Saeedi, M. and Sedighi, M. and Zamani, M.S.}, title = {A novel synthesis algorithm for reversible circuits}, journal = {Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on}, year = {2007}, pages = {65 -68}, doi = {http://dx.doi.org/10.1109/ICCAD.2007.4397245} }
Saeedi, M.; Zamani, M. & Sedighi, M.	On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement [Abstract] [BibTeX]	2007	VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on , pp. 428 -436	inproceedings	DOI
Abstract: In this paper, the behavior of substitution-based reversible circuit synthesis methods is studied. We analyze one of the most recent search-based synthesis algorithms to improve its quality by adding some new non-trivial substitutions. Furthermore, it is shown that the order of factor substitution affects the depth of search tree significantly. In addition, we consider the number of terms in positive polarity Reed-Muller (PPRM) expansions during factor substitution to show that some local increases in the number of terms may lead to better final synthesis results. Besides, the behavior of depth-first search (DFS) and breadth-first search (BFS) synthesis algorithms are investigated. It is demonstrated that BFS has more effects on the quality of results and sometimes leads to shorter runtime. Based on these properties, a new hybrid DFS/BFS synthesis algorithm is proposed. Our experiments show the efficiency of this algorithm
BibTeX: @inproceedings{2007_Saeedia, author = {Saeedi, M. and Zamani, M.S. and Sedighi, M.}, title = {On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement}, journal = {VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on}, year = {2007}, pages = {428 -436}, doi = {http://dx.doi.org/10.1109/ISVLSI.2007.72} }
Thapliyal, H. & Vinod, A.	Designing Efficient Online Testable Reversible Adders With New Reversible Gate [Abstract] [BibTeX]	2007	Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , pp. 1085 -1088	inproceedings	DOI
Abstract: Reversible logic is emerging as a promising computing paradigm having its applications in low power VLSI design, quantum computing, nanotechnology and optical computing. In this paper, a new 4 times 4 reversible gate termed `OTG' (online testable gate) is proposed suitable for online testability in reversible logic circuits. OTG can also work singly as a reversible full adder with a bare minimum of two garbage outputs. OTG is shown better than the recently proposed R1 gate (introduced for providing online testability in reversible logic circuits), in terms of computation complexity. The proposed reversible gate is combined with the existing 4 times 4 Feynman gate to design online testable reversible adders such as ripple carry adder, carry skip adder and BCD adder. The efficient reversible design of two pair rail checker is also shown in this paper. The testable reversible circuits proposed in this work are shown to be better than the recently proposed testable designs in terms of number of reversible gates, garbage outputs and unit delay
BibTeX: @inproceedings{2007_Thapliyal, author = {Thapliyal, H. and Vinod, A.P.}, title = {Designing Efficient Online Testable Reversible Adders With New Reversible Gate}, journal = {Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on}, year = {2007}, pages = {1085 -1088}, doi = {http://dx.doi.org/10.1109/ISCAS.2007.378198} }
Thapliyal, H. & Vinod, A.	Design of Reversible Sequential Elements With Feasibility of Transistor Implementation [Abstract] [BibTeX]	2007	Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , pp. 625 -628	inproceedings	DOI
Abstract: This paper presents the novel designs of reversible sequential circuits (latches and flip flops). The proposed reversible latches and flip flops are designed from reversible Fredkin, Feynman and Toffoli gates. Two new reversible gates called modified Fredkin gate (MFG) and modified Toffoli gate (MTG) are also proposed to design the optimized implementations. The proposed designs are better than the recently proposed ones in terms of number of reversible gates and garbage outputs. In order to reach towards the goal of transistor implementations of proposed reversible sequential circuits, transistor implementation of the existing Feynman gate, Fredkin gate, Toffoli gates as well as the proposed MTG and MFG are also proposed. The proposed transistor implementations are completely reversible in nature, i.e., suitable for both the forward and backward computation.
BibTeX: @inproceedings{2007_Thapliyala, author = {Thapliyal, H. and Vinod, A.P.}, title = {Design of Reversible Sequential Elements With Feasibility of Transistor Implementation}, journal = {Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on}, year = {2007}, pages = {625 -628}, doi = {http://dx.doi.org/10.1109/ISCAS.2007.378815} }
Wille, R. & Grosse, D.	Fast exact toffoli network synthesis of reversible logic [Abstract] [BibTeX]	2007	Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on , pp. 60 -64	inproceedings	DOI
Abstract: The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of generalized Toffoli networks are considered. We present an improvement of an existing synthesis approach that is based on Boolean Satisfiability. Furthermore, the principle limits of the original and the improved approach are shown. Then, we propose a new method using problem specific knowledge during the synthesis process to overcome these limits. Experimental results demonstrate improvements of the overall synthesis time up to four orders of magnitude.
BibTeX: @inproceedings{2007_Wille, author = {Wille, R. and Grosse, D.}, title = {Fast exact toffoli network synthesis of reversible logic}, journal = {Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on}, year = {2007}, pages = {60 -64}, doi = {http://dx.doi.org/10.1109/ICCAD.2007.4397244} }
Yang, G.; Song, X.; Perkowski, M.; Hung, W.; Biamonte, J. & Tang, Z.	Four-level realisation of 3-qubit reversible functions [Abstract] [BibTeX]	2007	Computers Digital Techniques, IET Vol. 1 (4) , pp. 382 -388	article	DOI
Abstract: Two questions have been addressed here: how many logic levels are necessary to synthesise a specific instance of a reversible circuit, and how much better to have large gate libraries, and what gates should be required in libraries. Group theory is applied to 3-bit reversible gate synthesis to create a library useful in hierarchical design. It has been shown that arbitrary 3-bit reversible circuit can be synthesised with four-logic levels, using this new gate library. The respective universal library for the four-level synthesis is constructed and optimised it on the level of nuclear magnetic resonance pulses. A very fast algorithm to synthesise arbitrary 3-bit reversible function to gates from our library is also presented. The algorithm demonstrates dramatic speed benefit and results in a maximum of four-level circuit for arbitrary 3-bit reversible function. The gates are optimised on the level of pulses to decrease their cost and allow for objective comparison with standard CNOT, NOT, Toffoli gates (CNT) circuits. This library guarantees a four-level circuit for any 3-qubit reversible function and is also intended to be used in a hierarchical design of larger circuits.
BibTeX: @article{2007_Yang, author = {Yang, G. and Song, X. and Perkowski, M.A. and Hung, W.N.N. and Biamonte, J. and Tang, Z.}, title = {Four-level realisation of 3-qubit reversible functions}, journal = {Computers Digital Techniques, IET}, year = {2007}, volume = {1}, number = {4}, pages = {382 -388}, doi = {http://dx.doi.org/10.1049/iet-cdt:20060097} }
Zilic, Z.; Radecka, K. & Kazamiphur, A.	Reversible Circuit Technology Mapping from Non-reversible Specifications [Abstract] [BibTeX]	2007	Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07 , pp. 1 -6	inproceedings	DOI
Abstract: This paper considers the synthesis of reversible circuits directly from an irreversible specification, with no need for producing a reversible embedding first. The authors present a feasible methodology for realizing the networks of reversible gates, in a manner that builds on the classical technology mapping. We do not restrict ourselves to the restricted notion of realizing permutation functions, and construct reversible implementations where extraneous signals are efficiently reused for overcoming the inherent fanout limitation
BibTeX: @inproceedings{2007_Zilic, author = {Zilic, Z. and Radecka, K. and Kazamiphur, A.}, title = {Reversible Circuit Technology Mapping from Non-reversible Specifications}, journal = {Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07}, year = {2007}, pages = {1 -6}, doi = {http://dx.doi.org/10.1109/DATE.2007.364652} }
Chowdhury, A.; Nazmul, R. & Hasan babu, H.	A new approach to synthesize multiple-output functions using reversible programmable logic array [Abstract] [BibTeX]	2006	VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on , pp. 6 pp.	inproceedings	DOI
Abstract: In this paper, a new realization for logic functions, namely reversible programmable logic array (RPLA), has been proposed. The proposed realization has the advantage of regularity as compared to the existing non-PLA reversible realizations. A minimization technique is also presented along with the realization of reversible PLA. Experimental results are also shown for benchmark functions for the above realization.
BibTeX: @inproceedings{2006_Chowdhury, author = {Chowdhury, A.R. and Nazmul, R. and Hasan babu, H.Md.}, title = {A new approach to synthesize multiple-output functions using reversible programmable logic array}, journal = {VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on}, year = {2006}, pages = { 6 pp.}, doi = {http://dx.doi.org/10.1109/VLSID.2006.18} }
Frank, M.P.	Reversible Computing and Truly Adiabatic Circuits: Truly Adiabatic Circuits: The Next Great Challenge for Digital Engineering [Abstract] [BibTeX]	2006	Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on , pp. 31 -38	inproceedings	DOI
Abstract: This paper provides a brief review of the energy dissipation problem in conventional FET-based logic. Some alternative device switching principles that might help with this problem in the relatively near term are described. Fundamental limits to dissipation that apply to any non-energy-recovering digital technology are described. Elements required as part of any long-term solution (i.e. adiabatic switching, reversible logic, and resonant clocking) are discussed
BibTeX: @inproceedings{2006_Frank, author = {Michael P. Frank}, title = {Reversible Computing and Truly Adiabatic Circuits: Truly Adiabatic Circuits: The Next Great Challenge for Digital Engineering}, journal = {Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on}, year = {2006}, pages = {31 -38}, doi = {http://dx.doi.org/10.1109/DCAS.2006.321027} }
GroBe, D.; Chen, X. & Drechsler, R.	Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability [Abstract] [BibTeX]	2006	Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on , pp. 51 -54	inproceedings	DOI
Abstract: Compact synthesis result for reversible logic is of major interest in low-power design and quantum computing. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean satisfiability (SAT) instances. Such an instance is satisfiable iff there exists a network representation with d gates. Thus we can guarantee minimality. For a set of benchmarks experimental results are given
BibTeX: @inproceedings{2006_GroBe, author = {Daniel GroBe and Xiaobo Chen and Rolf Drechsler}, title = {Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability}, journal = {Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on}, year = {2006}, pages = {51 -54}, doi = {http://dx.doi.org/10.1109/DCAS.2006.321031} }
Guan, Z.; Qin, X.; Ge, Z. & Zhang, Y.	Reversible Synthesis with Minimum logic function [Abstract] [BibTeX]	2006	Computational Intelligence and Security, 2006 International Conference on Vol. 2 , pp. 968 -971	inproceedings	DOI
Abstract: A first practical logic function reversible synthesis method has been presented. In this method, minimizing a standard logic function for obtained a SOP of optimization in our approach previously. This efficient conversion between SOP and fixed polarity Reed-Muller (FPRM) forms. The results show that the algorithm is efficient in terms of time and space. We also proposed the synthesis algorithm for reversible functions. It uses fixed polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. Some examples of NCMC benchmarks with a large number of variables were presented to demonstrate the suitability of the algorithm for synthesizing complex functions
BibTeX: @inproceedings{2006_Guan, author = {Zhijin Guan and Xiaolin Qin and Ziming Ge and Yiqing Zhang}, title = {Reversible Synthesis with Minimum logic function}, journal = {Computational Intelligence and Security, 2006 International Conference on}, year = {2006}, volume = {2}, pages = {968 -971}, doi = {http://dx.doi.org/10.1109/ICCIAS.2006.295405} }
Gupta, P.; Agrawal, A. & Jha, N.	An Algorithm for Synthesis of Reversible Logic Circuits [Abstract] [BibTeX]	2006	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 25 (11) , pp. 2317 -2330	article	DOI
Abstract: Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25
BibTeX: @article{2006_Gupta, author = {Gupta, P. and Agrawal, A. and Jha, N.K.}, title = {An Algorithm for Synthesis of Reversible Logic Circuits}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2006}, volume = {25}, number = {11}, pages = {2317 -2330}, doi = {http://dx.doi.org/10.1109/TCAD.2006.871622} }
Hari, S.K.S.; Shroff, S.; Mahammad, S.N. & Kamakoti, V.	Efficient Building Blocks for Reversible Sequential Circuit Design [Abstract] [BibTeX]	2006	Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on Vol. 1 , pp. 437 -441	inproceedings	DOI
Abstract: Reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. In this paper we propose a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.
BibTeX: @inproceedings{2006_Hari, author = {Hari, Siva Kumar Sastry and Shroff, Shyam and Mahammad, Sk. Noor and Kamakoti, V.}, title = {Efficient Building Blocks for Reversible Sequential Circuit Design}, journal = {Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on}, year = {2006}, volume = {1}, pages = {437 -441}, doi = {http://dx.doi.org/10.1109/MWSCAS.2006.382092} }
Hu, J.; Ma, G. & Feng, G.	Efficient Algorithm for Positive-polarity Reed-muller Expansions of reversible circuits [Abstract] [BibTeX]	2006	Microelectronics, 2006. ICM '06. International Conference on , pp. 63 -66	inproceedings	DOI
Abstract: In this paper, we build mathematical modeling for reversible circuits and derive required parameters of cost function from this modeling. The heuristic algorithm plots out reversible circuit into some partitions, uses a priority queue based on search tree and explores candidate components at each partition in order of utilization ratio. We demonstrate that using this heuristic, path delay can be reduced by 8% compared to existing synthesis method. The improvements increase for strict delay constraints making synthesis especially important for high performance and a large number of inputs and outputs designs.
BibTeX: @inproceedings{2006_Hu, author = {Jing Hu and GuangSheng Ma and Gang Feng}, title = {Efficient Algorithm for Positive-polarity Reed-muller Expansions of reversible circuits}, journal = {Microelectronics, 2006. ICM '06. International Conference on}, year = {2006}, pages = {63 -66}, doi = {http://dx.doi.org/10.1109/ICM.2006.373267} }
Hung, W.; Song, X.; Yang, G.; Yang, J. & Perkowski, M.	Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis [Abstract] [BibTeX]	2006	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 25 (9) , pp. 1652 -1663	article	DOI
Abstract: This paper proposes an approach to optimally synthesize quantum circuits by symbolic reachability analysis, where the primary inputs and outputs are basis binary and the internal signals can be nonbinary in a multiple-valued domain. The authors present an optimal synthesis method to minimize quantum cost and some speedup methods with nonoptimal quantum cost. The methods here are applicable to small reversible functions. Unlike previous works that use permutative reversible gates, a lower level library that includes nonpermutative quantum gates is used here. The proposed approach obtains the minimum cost quantum circuits for Miller gate, half adder, and full adder, which are better than previous results. This cost is minimum for any circuit using the set of quantum gates in this paper, where the control qubit of 2-qubit gates is always basis binary. In addition, the minimum quantum cost in the same manner for Fredkin, Peres, and Toffoli gates is proven. The method can also find the best conversion from an irreversible function to a reversible circuit as a byproduct of the generality of its formulation, thus synthesizing in principle arbitrary multi-output Boolean functions with quantum gate library. This paper constitutes the first successful experience of applying formal methods and satisfiability to quantum logic synthesis
BibTeX: @article{2006_Hung, author = {Hung, W.N.N. and Xiaoyu Song and Guowu Yang and Jin Yang and Perkowski, M.}, title = {Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2006}, volume = {25}, number = {9}, pages = {1652 -1663}, doi = {http://dx.doi.org/10.1109/TCAD.2005.858352} }
Kaivani, A.; Alhosseini, A.; Gorgin, S. & Fazlali, M.	Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R [Abstract] [BibTeX]	2006	Information Technology, 2006. ICIT '06. 9th International Conference on , pp. 273 -276	inproceedings	DOI
Abstract: The binary coded decimal (BCD) encoding has always dominated the decimal arithmetic algorithms and their hardware implementation. Due to importance of decimal arithmetic, the decimal format defined in IEEE 754 floating point standard has been revisited. It uses densely packed decimal (DPD) encoding to store significant part of a decimal floating point number. Furthermore in recent years reversible logic has attracted the attention of engineers for designing low power CMOS circuits, as it is not possible to realize quantum computing without reversible logic implementation. This paper derives the reversible implementation of DPD converter to and from conventional BCD format using in IEEE754R.
BibTeX: @inproceedings{2006_Kaivani, author = {Kaivani, A. and Alhosseini, A.Z. and Gorgin, S. and Fazlali, M.}, title = {Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R}, journal = {Information Technology, 2006. ICIT '06. 9th International Conference on}, year = {2006}, pages = {273 -276}, doi = {http://dx.doi.org/10.1109/ICIT.2006.78} }
Ma, X.; Huang, J.; Metra, C. & Lombardi, F.	Testing Reversible 1D Arrays for Molecular QCA [Abstract] [BibTeX]	2006	Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on , pp. 71 -79	inproceedings	DOI
Abstract: Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption
BibTeX: @inproceedings{2006_Ma, author = {Ma, X. and Huang, J. and Metra, C. and Lombardi, F.}, title = {Testing Reversible 1D Arrays for Molecular QCA}, journal = {Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on}, year = {2006}, pages = {71 -79}, doi = {http://dx.doi.org/10.1109/DFT.2006.63} }
Maslov, D.	Efficient reversible and quantum implementations of symmetric Boolean functions [Abstract] [BibTeX]	2006	Circuits, Devices and Systems, IEE Proceedings - Vol. 153 (5) , pp. 467 -472	article	DOI
Abstract: It is a well-known fact in logic design that synthesis of some special classes of Boolean functions is often easier than the synthesis of a general unrestricted specification. In reversible logic, well-scaled synthesis methods with a reasonably small cost of the associated implementation have been found for only a few classes of functions. This includes synthesis of multiple-output symmetric and reversible linear functions. The author presents an efficient reversible/quantum synthesis method for the class of multiple-output symmetric functions. The method is purely theoretical, therefore its scaling on functions with a large number of inputs/outputs requires minimal resources. The author calculates garbage, i.e. the number of outputs that are not required by the function specification, the number of reversible gates, and the quantum cost of the presented implementations. The proposed approach is then applied to the synthesis of benchmark functions. Comparison of the designs to the previously reported implementations is favourable
BibTeX: @article{2006_Maslov, author = {Maslov, D.}, title = {Efficient reversible and quantum implementations of symmetric Boolean functions}, journal = {Circuits, Devices and Systems, IEE Proceedings -}, year = {2006}, volume = {153}, number = {5}, pages = {467 -472}, doi = {http://dx.doi.org/10.1049/ip-cds:20045213} }
Miller, D. & Thornton, M.	QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits [Abstract] [BibTeX]	2006	Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on , pp. 30 - 30	inproceedings	DOI
Abstract: In this paper, we present a novel structure, QuantumMultiple- valued Decision Diagrams (QMDD), specifically designed to represent and manipulate the matrices encountered in the specification of reversible and quantum gates and circuits, both binary and multiple-valued. QMDD use many common decision diagram techniques, ideas introduced in QuIDDPro and novel techniques introduced here. Building the QMDD for the matrices for individual gates and the subsequent construction of the QMDD for the matrix describing a circuit are discussed. A prototype C implementation is described and experimental results are given that show the new structure is a promising and compact representation for reversible and quantum logic circuits.
BibTeX: @inproceedings{2006_Miller, author = { Miller, D.M. and Thornton, M.A.}, title = {QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits}, journal = {Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on}, year = {2006}, pages = { 30 - 30}, doi = {http://dx.doi.org/10.1109/ISMVL.2006.35} }
Miller, D.; Thornton, M. & Goodman, D.	A Decision Diagram Package for Reversible and Quantum Circuit Simulation [Abstract] [BibTeX]	2006	Evolutionary Computation, 2006. CEC 2006. IEEE Congress on , pp. 2428 -2435	inproceedings	DOI
Abstract: This paper presents a decision diagram structure intended for the simulation and verification of reversible and quantum circuits. The structure is designed to efficiently represent the matrices describing reversible and quantum gate and circuit behaviour and takes advantage of key properties of those matrices. Algorithms are described for efficiently building the decision diagram representation directly from a gate without constructing the actual matrix and for performing matrix multiplication which is the fundamental operation to determine the function realized by a cascade of gates. Experimental results show the methods presented are applicable to large circuits at the state of the art in reversible and quantum synthesis and design.
BibTeX: @inproceedings{2006_Millera, author = {Miller, D.M. and Thornton, M.A. and Goodman, D.}, title = {A Decision Diagram Package for Reversible and Quantum Circuit Simulation}, journal = {Evolutionary Computation, 2006. CEC 2006. IEEE Congress on}, year = {2006}, pages = {2428 -2435}, doi = {http://dx.doi.org/10.1109/CEC.2006.1688610} }
Parhami, B.	Fault-Tolerant Reversible Circuits [Abstract] [BibTeX]	2006	Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on , pp. 1726 -1729	inproceedings	DOI
Abstract: Reversible hardware computation, that is, performing logic signal transformations in a way that allows the original input signals to be recovered from the produced outputs, is helpful in diverse areas such as quantum computing, low-power design, nanotechnology, optical information processing, and bioinformatics. We propose a paradigm for performing such reversible computations in a manner that renders a wide class of circuit faults readily detectable at the circuit's outputs. More specifically, we introduce a class of reversible logic gates (consisting of the well-known Fredkin gate and a newly defined Feynman double-gate) for which the parity of the outputs matches that of the inputs. Such parity-preserving reversible gates, when used with an arbitrary synthesis strategy for reversible logic circuits, allow any fault that affects no more than a single logic signal to be detectable at the circuit's primary outputs. We show the applicability of our design strategy by demonstrating how the well-known, and very useful, Toffoli gate can be synthesized from parity- preserving gates and apply the results to the design of a binary full-adder circuit, which is a versatile and widely used element in digital arithmetic processing.
BibTeX: @inproceedings{2006_Parhami, author = {Parhami, B.}, title = {Fault-Tolerant Reversible Circuits}, journal = {Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on}, year = {2006}, pages = {1726 -1729}, doi = {http://dx.doi.org/10.1109/ACSSC.2006.355056} }
Po-Leen Ooi, M.	Hardware implementation for face detection on Xilinx Virtex-II FPGA using the reversible component transformation colour space [Abstract] [BibTeX]	2006	Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on , pp. 6 pp. -46	inproceedings	DOI
Abstract: Face detection is the process of locating the position where faces are present in an image. Not all proposed face detection methods are suitable for direct hardware implementation. This paper explains a method that utilises the reversible component transformation (RCT) colour space and outlines its transition from a software- to hardware-based implementation. The hardware performance and efficiency of the RCT algorithm is examined using the Xilinx Virtex-II field programmable gate arrays (FPGA). Results show that there is almost negligible difference in performance after transition to hardware and its implementation on FPGA requires 255,416 NAND gates, which is only slightly more than twice the number of NAND gates of a basic video-in application
BibTeX: @inproceedings{2006_Po-LeenOoi, author = {Po-Leen Ooi, M.}, title = {Hardware implementation for face detection on Xilinx Virtex-II FPGA using the reversible component transformation colour space}, journal = {Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on}, year = {2006}, pages = {6 pp. -46}, doi = {http://dx.doi.org/10.1109/DELTA.2006.52} }
Rice, J.	A new look at reversible memory elements [Abstract] [BibTeX]	2006	Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on , pp. 4 pp.	inproceedings	DOI
Abstract: Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. We present an analysis of a basic memory element, the RS-latch, and a number of possible implementations. We then go on to introduce four reversible flip-flop designs based on the reversible RS-latch implementation
BibTeX: @inproceedings{2006_Rice, author = {Rice, J.E.}, title = {A new look at reversible memory elements}, journal = {Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on}, year = {2006}, pages = {4 pp.}, doi = {http://dx.doi.org/10.1109/ISCAS.2006.1692817} }
Thapliyal, H. & Zwolinski, M.	Reversible Logic to Cryptographic Hardware: A New Paradigm [Abstract] [BibTeX]	2006	Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on Vol. 1 , pp. 342 -346	inproceedings	DOI
Abstract: Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this type of attack, this paper proposes the use of reversible logic for designing the ALU of a cryptosystem. Ideally, reversible circuits dissipate zero energy. Thus, it would be of great significance to apply reversible logic to designing secure cryptosystems. As far as is known, this is the first attempt to apply reversible logic to developing secure cryptosystems. In a prototype of a reversible ALU for a crypto-processor, reversible designs of adders and Montgomery multipliers are presented. The reversible designs of a carry propagate adder, four-to-two and five-to-two carry save adders are presented using a reversible TSG gate. One of the important properties of the TSG gate is that it can work singly as a reversible full adder. In order to design the reversible Montgomery multiplier, novel reversible sequential circuits are also proposed which are integrated with the proposed adders to design a reversible modulo multiplier. It is intended that this paper will provide a starting point for developing cryptosystems secure against DPA attacks.
BibTeX: @inproceedings{2006_Thapliyal, author = {Thapliyal, Himanshu and Zwolinski, Mark}, title = {Reversible Logic to Cryptographic Hardware: A New Paradigm}, journal = {Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on}, year = {2006}, volume = {1}, pages = {342 -346}, doi = {http://dx.doi.org/10.1109/MWSCAS.2006.382067} }
Thapliyal, H. & Vinod, A.	Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures [Abstract] [BibTeX]	2006	Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on , pp. 418 -421	inproceedings	DOI
Abstract: Reversible logic is emerging as a promising technology with applications in design of low power arithmetic and data path units for digital signal processing (DSP), quantum computing, nanotechnology, and optical computing. In this paper, the transistor realization of a new 4*4 reversible gate called "TSG" gate is presented. The proposed TSG gate has the ability to operate as a reversible full adder i.e. reversible full adder is implemented using a single gate. The transistor realizations of 1-bit reversible full adder, reversible ripple carry adder and reversible carry skip adder are also presented. In order to have the reduced transistor overhead of reversible carry skip adder, its modified design has been proposed. We also demonstrate a method to minimize the overhead in transistor implementation of reversible arithmetic units. The transistor implementation of reversible arithmetic circuits presented in this paper finds extensive applications in computationally intensive DSP tasks
BibTeX: @inproceedings{2006_Thapliyala, author = {Thapliyal, H. and Vinod, A.P.}, title = {Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures}, journal = {Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on}, year = {2006}, pages = {418 -421}, doi = {http://dx.doi.org/10.1109/APCCAS.2006.342478} }
Thapliyal, H.; Kotiyal, S. & Srinivas, M.	Novel BCD adders and their reversible logic implementation for IEEE 754r format [Abstract] [BibTeX]	2006	VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on , pp. 6 pp.	inproceedings	DOI
Abstract: IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel BCD adders called carry skip and carry look-ahead BCD adders respectively. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the conventional BCD adder as the well as the proposed carry skip BCD adder using a recently proposed TSG gate. Furthermore, a new reversible gate called TS-3 is also being proposed and it has been shown that the proposed reversible logic implementation of the BCD adders is much better compared to recently proposed one, in terms of number of reversible gates used and garbage outputs produced. The reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU.
BibTeX: @inproceedings{2006_Thapliyalb, author = {Thapliyal, H. and Kotiyal, S. and Srinivas, M.B.}, title = {Novel BCD adders and their reversible logic implementation for IEEE 754r format}, journal = {VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on}, year = {2006}, pages = { 6 pp.}, doi = {http://dx.doi.org/10.1109/VLSID.2006.122} }
Thapliyal, H.; Arabnia, H. & Vinod, A.	Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation [Abstract] [BibTeX]	2006	Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on Vol. 2 , pp. 438 -442	inproceedings	DOI
Abstract: In this paper, the authors propose the idea of a combined integer and floating point multiplier (CIFM) for FPGAs. The authors propose the replacement of existing 18times18 dedicated multipliers in FPGAs with dedicated 24times24 multipliers designed with small 4times4 bit multipliers. It is also proposed that for every dedicated 24times24 bit multiplier block designed with 4times4 bit multipliers, four redundant 4times4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the proposed CIFM reconfigurability at run time is also provided resulting in low power. The major source of motivation for providing the dedicated 24times24 bit multiplier stems from the fact that single precision floating point multiplier requires 24times24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24times24 bit multiplier (implemented with 4times4 bit multiply modules) will ideally suit this purpose, making FPGAs more suitable for integer as well floating point operations. A dedicated 4times4 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. The reversible CIFM designed and proposed here will form the basis of the completely reversible FPGAs.
BibTeX: @inproceedings{2006_Thapliyalc, author = {Thapliyal, H. and Arabnia, H.R. and Vinod, A.P.}, title = {Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation}, journal = {Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on}, year = {2006}, volume = {2}, pages = {438 -442}, doi = {http://dx.doi.org/10.1109/MWSCAS.2006.382306} }
Thapliyal, H. & Gupta, S.	Design of Novel Reversible Carry Look-Ahead BCD Subtractor [Abstract] [BibTeX]	2006	Information Technology, 2006. ICIT '06. 9th International Conference on , pp. 253 -258	inproceedings	DOI
Abstract: IEEE 754r is the ongoing revision to the IEEE 754 floating point standard. A major enhancement to the standard is the addition of decimal format, thus the design of BCD arithmetic units is likely to get significant attention. Firstly, this paper introduces a novel carry look-ahead BCD adder and then builds a novel carry look-ahead BCD subtracter based on it. Secondly, it introduces the reversible logic implementation of the proposed carry look-ahead BCD subtracter. We have tried to design the reversible logic implementation of the BCD Subtracter optimal in terms of number of reversible gates used and garbage outputs produced. Thus, the proposed work will be of significant value as the technologies mature.
BibTeX: @inproceedings{2006_Thapliyald, author = {Thapliyal, H. and Gupta, S.K.}, title = {Design of Novel Reversible Carry Look-Ahead BCD Subtractor}, journal = {Information Technology, 2006. ICIT '06. 9th International Conference on}, year = {2006}, pages = {253 -258}, doi = {http://dx.doi.org/10.1109/ICIT.2006.44} }
Vasudevan, D.; Lala, P.; Di, J. & Parkerson, J.	Reversible-logic design with online testability [Abstract] [BibTeX]	2006	Instrumentation and Measurement, IEEE Transactions on Vol. 55 (2) , pp. 406 - 414	article	DOI
Abstract: Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.
BibTeX: @article{2006_Vasudevan, author = {Vasudevan, D.P. and Lala, P.K. and Jia Di and Parkerson, J.P.}, title = {Reversible-logic design with online testability}, journal = {Instrumentation and Measurement, IEEE Transactions on}, year = {2006}, volume = {55}, number = {2}, pages = { 406 - 414}, doi = {http://dx.doi.org/10.1109/TIM.2006.870319} }
Yuan, D.; BaiYan; WenTao, L. & Yi, G.	Research and implementation of reversible logic synthesis algorithmin digital system [Abstract] [BibTeX]	2006	Computer-Aided Industrial Design and Conceptual Design, 2006. CAIDCD '06. 7th International Conference on , pp. 1 -7	inproceedings	DOI
Abstract: The reversible logic synthesis is one of the important methods in the digital system's fault testing and investigating area. As the designing and manufacturing technique of vary large scale digital systems fast develops, under current computer conditions, how to rapidly and accurately implement the reversible logic synthesis of a vary large scale digital systems is a knotty problem that the computer aided logic design researchers have been difficult to resolve and can not evade. Based on deeply studying logical synthesis theories, this paper presented an algorithm called iterative intersection of subset, improved reversible logic synthesis algorithm, and made efficiency experiments of the algorithm. The outcome showed that the reversible logic synthesis performance of vary large scale digital systems using iterative intersection algorithm is markedly superior to the traditional logical synthesis algorithm
BibTeX: @inproceedings{2006_Yuan, author = {Ding Yuan and BaiYan and Lu WenTao and Guo Yi}, title = {Research and implementation of reversible logic synthesis algorithmin digital system}, journal = {Computer-Aided Industrial Design and Conceptual Design, 2006. CAIDCD '06. 7th International Conference on}, year = {2006}, pages = {1 -7}, doi = {http://dx.doi.org/10.1109/CAIDCD.2006.329380} }
Zhong, J. & Muzio, J.	Using Crosspoint Faults in Simplifying Toffoli Networks [Abstract] [BibTeX]	2006	Circuits and Systems, 2006 IEEE North-East Workshop on , pp. 129 -132	inproceedings	DOI
Abstract: Reversible logic computing is a rapidly developing research area. The synthesis of reversible logic and finding minimum-cost circuits are very important issues in this area. In this paper, the authors introduce a new method to detect redundancy in a reversible circuit and, by deleting redundant portions; the authors can simplify the circuit. This approach is based on a new fault model, the crosspoint fault, for reversible logic circuits. The authors show that multiple crosspoint faults are useful in synthesizing reversible circuits implemented with Toffoli networks. Experimental results from benchmark circuits show that some of the circuits can be simplified by deleting all pairs of independent multiple crosspoint faults, with the resulting circuit being functionally equivalent to the original
BibTeX: @inproceedings{2006_Zhong, author = {Jing Zhong and Muzio, J.C.}, title = {Using Crosspoint Faults in Simplifying Toffoli Networks}, journal = {Circuits and Systems, 2006 IEEE North-East Workshop on}, year = {2006}, pages = {129 -132}, doi = {http://dx.doi.org/10.1109/NEWCAS.2006.250942} }
Altenkirch, T. & Grattage, J.	A functional quantum programming language [Abstract] [BibTeX]	2005	Logic in Computer Science, 2005. LICS 2005. Proceedings. 20th Annual IEEE Symposium on , pp. 249 - 258	inproceedings	DOI
Abstract: We introduce the language QML, a functional language for quantum computations on finite types. Its design is guided by its categorical semantics: QML programs are interpreted by morphisms in the category FQC of finite quantum computations, which provides a constructive semantics of irreversible quantum computations realisable as quantum gates. QML integrates reversible and irreversible quantum computations in one language, using first order strict linear logic to make weakenings explicit. Strict programs are free from decoherence and hence preserve superpositions and entanglement -which is essential for quantum parallelism.
BibTeX: @inproceedings{2005_Altenkirch, author = {Altenkirch, T. and Grattage, J.}, title = {A functional quantum programming language}, journal = {Logic in Computer Science, 2005. LICS 2005. Proceedings. 20th Annual IEEE Symposium on}, year = {2005}, pages = { 249 - 258}, doi = {http://dx.doi.org/10.1109/LICS.2005.1} }
Babu, H. & Chowdhury, A.	Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder [Abstract] [BibTeX]	2005	VLSI Design, 2005. 18th International Conference on , pp. 255 - 260	inproceedings	DOI
Abstract: In this paper, we have proposed a design technique for the reversible circuit of binary coded decimal (BCD) adder. The proposed circuit has the ability to add two 4-bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.
BibTeX: @inproceedings{2005_Babu, author = {Babu, H.M.H. and Chowdhury, A.R.}, title = {Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder}, journal = {VLSI Design, 2005. 18th International Conference on}, year = {2005}, pages = { 255 - 260}, doi = {http://dx.doi.org/10.1109/ICVD.2005.74} }
Chakraborty, A.	Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays [Abstract] [BibTeX]	2005	VLSI Design, 2005. 18th International Conference on , pp. 249 - 254	inproceedings	DOI
Abstract: Reversibility is of interest in the design of very low-power circuits; it is essential for quantum computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at fault model (both single stuck-at fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets TUTS such that each C(n) has a unique test set T(n) in TUTS that detects all F-type faults in every member of C(n). We show that if k ge; 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n2 + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model; this number is determined by the size of the RILA cell's state table.
BibTeX: @inproceedings{2005_Chakraborty, author = {Chakraborty, A.}, title = {Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays}, journal = {VLSI Design, 2005. 18th International Conference on}, year = {2005}, pages = { 249 - 254}, doi = {http://dx.doi.org/10.1109/ICVD.2005.158} }
Frank, M.	Approaching the physical limits of computing [Abstract] [BibTeX]	2005	Multiple-Valued Logic, 2005. Proceedings. 35th International Symposium on , pp. 168 - 185	inproceedings	DOI
Abstract: As logic device sizes shrink towards the nanometer scale, a number of important physical limits threaten to soon halt further improvements in computer performance per unit cost. However, the near-term limits are not truly fundamental, and may be avoided by making radical changes to the physical and logical architecture of computers. In particular, certain assumed limits to the energy efficiency of computers have never been rigorously proven, and may be circumvented using physical mechanisms that recover and reuse signal energies with efficiency approaching 100%. However, this concept, called reversible computing, imposes tight constraints on the design of the machine at all levels from physics to algorithms. We review the physical and architectural requirements that must be met if real machines are to break through the barriers preventing further progress, and approach the true fundamental physical limits to computing.
BibTeX: @inproceedings{2005_Frank, author = {Frank, M.P.}, title = {Approaching the physical limits of computing}, journal = {Multiple-Valued Logic, 2005. Proceedings. 35th International Symposium on}, year = {2005}, pages = { 168 - 185}, doi = {http://dx.doi.org/10.1109/ISMVL.2005.9} }
Khazamipour, A. & Radecka, K.	Adiabatic implementation of reversible logic [Abstract] [BibTeX]	2005	Circuits and Systems, 2005. 48th Midwest Symposium on , pp. 291 - 294 Vol. 1	inproceedings	DOI
Abstract: Reversible circuits are applicable to nanotechnology, quantum and optical computing, as well as to reducing power in CMOS implementations. In adiabatic circuits, current is restricted to flow across devices with low voltage drop and the energy stored on their capacitors is recycled. We first introduce a new reversible gate capable to realize functions AND, OR or NAND, NOR. Next, we use reversible energy recovery logic (RERL), with eight-phase clocking scheme for designing of basic reversible gates. With RERL concept we can meet Bennett (Bennett, 1973) theorem and implement any reversible logic gate or circuit.
BibTeX: @inproceedings{2005_Khazamipour, author = {Khazamipour, A. and Radecka, K.}, title = {Adiabatic implementation of reversible logic}, journal = {Circuits and Systems, 2005. 48th Midwest Symposium on}, year = {2005}, pages = { 291 - 294 Vol. 1}, doi = {http://dx.doi.org/10.1109/MWSCAS.2005.1594096} }
Kim, S.; Ziesler, C. & Papaefthymiou, M.	Charge-recovery computing on silicon [Abstract] [BibTeX]	2005	Computers, IEEE Transactions on Vol. 54 (6) , pp. 651 - 659	article	DOI
Abstract: Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV2 rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, exploring VLSI designs that use reversible logic and adiabatic switching to preserve information and achieve nearly zero power dissipation as operating frequencies approach zero. Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. Although their origins can be traced back to the early adiabatic circuits, these charge-recovering systems approach energy recycling from a more practical angle, shedding reversibility to achieve operating frequencies in the hundreds of MHz with relatively low overhead. Among other charge-recovery designs, researchers have demonstrated microcontrollers, standard-cell ASICs, SRAMs, LCD panel drivers, I/O drivers, and multiGHz clock networks. In this paper, we present an overview of the field and focus on two chip designs that highlight some of the promising charge recovering techniques in practice.
BibTeX: @article{2005_Kim, author = {Suhwan Kim and Ziesler, C.H. and Papaefthymiou, M.C.}, title = {Charge-recovery computing on silicon}, journal = {Computers, IEEE Transactions on}, year = {2005}, volume = {54}, number = {6}, pages = { 651 - 659}, doi = {http://dx.doi.org/10.1109/TC.2005.91} }
Kim, S. & lk Chae, S.	Complexity reduction in an nRERL microprocessor [Abstract] [BibTeX]	2005	Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on , pp. 180 - 185	inproceedings
Abstract: We describe an adiabatic microprocessor implemented with a reversible logic, nRERL (Lim et al., 2000). We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption. We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25 mu;m CMOS technology. Its minimum energy consumption of 4.67 mu;A/MHz was measured at Vdd=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version.
BibTeX: @inproceedings{2005_Kima, author = {Seokkee Kim and Soo-lk Chae}, title = {Complexity reduction in an nRERL microprocessor}, journal = {Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on}, year = {2005}, pages = { 180 - 185} }
Maslov, D.; Young, C.; Miller, D. & Dueck, G.	Quantum circuit simplification using templates [Abstract] [BibTeX]	2005	Design, Automation and Test in Europe, 2005. Proceedings , pp. 1208 - 1213 Vol. 2	inproceedings	DOI
Abstract: Optimal synthesis of quantum circuits is intractable and heuristic methods must be employed. Templates are a general approach to reversible quantum circuit simplification. We consider the use of templates to simplify a quantum circuit initially found by other means. We present and analyze templates in the general case, and then provide particular details for circuits composed of NOT, CNOT and controlled-sqrt-of-NOT gates. We introduce templates for this set of gates and apply them to simplify both known quantum realizations of Toffoli gates and circuits found by earlier heuristic Fredkin and Toffoli gate synthesis algorithms. While the number of templates is quite small, the reduction in quantum cost is often significant.
BibTeX: @inproceedings{2005_Maslov, author = {Maslov, D. and Young, C. and Miller, D.M. and Dueck, G.W.}, title = {Quantum circuit simplification using templates}, journal = {Design, Automation and Test in Europe, 2005. Proceedings}, year = {2005}, pages = { 1208 - 1213 Vol. 2}, doi = {http://dx.doi.org/10.1109/DATE.2005.249} }
Maslov, D.; Dueck, G. & Miller, D.	Synthesis of Fredkin-Toffoli reversible networks [Abstract] [BibTeX]	2005	Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Vol. 13 (6) , pp. 765 - 769	article	DOI
Abstract: Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate and the Fredkin gate. We present a method that synthesizes a network with these gates in two steps. First, our synthesis algorithm finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead. Next we apply transformations that reduce the number of gates in the network. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence of gates in the network to be reduced matches a sequence of gates comprising more than half of a template, then a transformation that reduces the gate count can be applied. We have synthesized all three input, three output reversible functions and here compare our results to the optimal results. We also present the results of applying our synthesis tool to obtain networks for a number of benchmark functions.
BibTeX: @article{2005_Maslova, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Synthesis of Fredkin-Toffoli reversible networks}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, year = {2005}, volume = {13}, number = {6}, pages = { 765 - 769}, doi = {http://dx.doi.org/10.1109/TVLSI.2005.844284} }
Maslov, D.; Dueck, G. & Miller, D.	Toffoli network synthesis with templates [Abstract] [BibTeX]	2005	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 24 (6) , pp. 807 - 817	article	DOI
Abstract: Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired function. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the above synthesis approach. We present a basic method and, based on that, a bidirectional synthesis algorithm which produces a network of Toffoli gates realizing a given reversible specification. An asymptotically optimal modification of the basic synthesis algorithm employing generalized mEXOR gates is also presented. Transformations are then applied using template matching. The basis for a template is a network of gates that realizes the identity function. If a sequence of gates in the synthesized network matches a sequence comprised of more than half the gates in a template, then a transformation using the remaining gates in the template can be applied resulting in a reduction in the gate count for the synthesized network. All templates with up to six gates are described in this paper. Experimental results including an exhaustive examination of all 3-variable reversible functions and a collection of benchmark problems are presented. The paper concludes with suggestions for further research.
BibTeX: @article{2005_Maslovb, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Toffoli network synthesis with templates}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2005}, volume = {24}, number = {6}, pages = { 807 - 817}, doi = {http://dx.doi.org/10.1109/TCAD.2005.847911} }
Thapliyal, H. & Srinivas, M.	Novel design and reversible logic synthesis of multiplexer based full adder and multipliers [Abstract] [BibTeX]	2005	Circuits and Systems, 2005. 48th Midwest Symposium on , pp. 1593 - 1596 Vol. 2	inproceedings	DOI
Abstract: Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3 times;3 reversible gate termed TKS gate having two of its outputs working as 2:1 multiplexer. The proposed TKS gate is used to design a reversible half adder and is further used to design multiplexer based reversible full adder. The multiplexer based full adder is further used to design reversible 4 times;4 Array and modified Baugh Wooley multipliers. A novel 4 times;4 multiplier architecture with reversible logic is also proposed in which the partial products can be generated in parallel and their additions are reduced to logarithmic steps. In the proposed multiplier, all the operations are decomposed into levels, thereby significantly reducing the power consumption through a control circuitry which will switch off those levels which are not active. Thus, this work provides the initial threshold to building of complex systems which can execute more complicated operations. The reversible circuits designed and proposed in this paper form the basis for an ALU of a primitive quantum CPU.
BibTeX: @inproceedings{2005_Thapliyal, author = {Thapliyal, H. and Srinivas, M.B.}, title = {Novel design and reversible logic synthesis of multiplexer based full adder and multipliers}, journal = {Circuits and Systems, 2005. 48th Midwest Symposium on}, year = {2005}, pages = { 1593 - 1596 Vol. 2}, doi = {http://dx.doi.org/10.1109/MWSCAS.2005.1594420} }
Thapliyal, H. & Srinivas, M.	Novel Reversible `TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU [Abstract] [BibTeX]	2005	Information, Communications and Signal Processing, 2005 Fifth International Conference on , pp. 1425 -1429	inproceedings	DOI
Abstract: In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper utilizes a new 4*4 reversible gate called TSG gate to build the components of a primitive reversible/quantum ALU. The most significant aspect of the TSG gate is that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only. A Novel reversible 4:2 compressor is also designed from the TSG gate which is later used to design a novel 8times8 reversible Wallace tree multiplier. It is proved that the adder, 4:2 compressor and multiplier architectures designed using the TSG gate are better than their counterparts available in literature, in terms of number of reversible gates and garbage outputs. This is perhaps, the first attempt to design a reversible 4:2 compressor and a reversible Wallace tree multiplier as far as existing literature and our knowledge is concerned. Thus, this paper provides an initial threshold to build more complex systems which can execute complicated operations using reversible logic
BibTeX: @inproceedings{2005_Thapliyala, author = {Thapliyal, H. and Srinivas, M.B.}, title = {Novel Reversible `TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU}, journal = {Information, Communications and Signal Processing, 2005 Fifth International Conference on}, year = {2005}, pages = {1425 -1429}, doi = {http://dx.doi.org/10.1109/ICICS.2005.1689293} }
Yang, G.; Song, X.; Hung, W. & Perkowski, M.	Bi-direction synthesis for reversible circuits [Abstract] [BibTeX]	2005	VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on , pp. 14 - 19	inproceedings	DOI
Abstract: Quantum computing is one of the most promising emerging technologies of the future. Reversible circuits are an important class of quantum circuits. In this paper, we investigate the problem of optimally synthesizing four-qubit reversible circuits. We present an enhanced bidirectional synthesis approach. Due to the super-exponential increase on the memory requirement, all the existing methods can only perform four steps for the CNP (Control-Not gate, NOT gate, and Peres gate) library. Our novel method can achieve 12 steps. As a result, we augment the number of circuits that can be optimally synthesized by over 5*106 times. Moreover, our approach is faster than the existing approaches by orders of magnitude. The promising experimental results demonstrate the effectiveness of our approach.
BibTeX: @inproceedings{2005_Yang, author = {Guowu Yang and Xiaoyu Song and Hung, W.N.N. and Perkowski, M.A.}, title = {Bi-direction synthesis for reversible circuits}, journal = {VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on}, year = {2005}, pages = { 14 - 19}, doi = {http://dx.doi.org/10.1109/ISVLSI.2005.21} }
Yang, G.; Song, X.; Hung, W. & Perkowski, M.	Fast synthesis of exact minimal reversible circuits using group theory [Abstract] [BibTeX]	2005	Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific Vol. 2 , pp. 1002 - 1005 Vol. 2	inproceedings	DOI
Abstract: We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory problems, we use the powerful algebraic software GAP to solve such problems. Our algorithms are not only able to minimize for arbitrary cost functions of gates, but also orders of magnitude faster than the existing approaches to reversible logic synthesis. In addition, we show that the Peres gate is a better choice than the standard Toffoli gate in libraries of universal reversible gates.
BibTeX: @inproceedings{2005_Yanga, author = {Guowu Yang and Xiaoyu Song and Hung, W.N.N. and Perkowski, M.A.}, title = {Fast synthesis of exact minimal reversible circuits using group theory}, journal = {Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific}, year = {2005}, volume = {2}, pages = { 1002 - 1005 Vol. 2}, doi = {http://dx.doi.org/10.1109/ASPDAC.2005.1466509} }
Yang, G.; Hung, W.; Song, X. & Perkowski, M.	Exact synthesis of 3-qubit quantum circuits from non-binary quantum gates using multiple-valued logic and group theory [Abstract] [BibTeX]	2005	Design, Automation and Test in Europe, 2005. Proceedings , pp. 434 - 435 Vol. 1	inproceedings	DOI
Abstract: We propose an approach to optimally synthesize quantum circuits from non-permutative quantum gates such as controlled-square-root-of-not (i.e., controlled-V). Our approach reduces the synthesis problem to multiple-valued optimization and uses group theory. We devise a novel technique that transforms the quantum logic synthesis problem from a multi-valued constrained optimization problem to a group permutation problem. The transformation enables us to utilize group theory to exploit the properties of the synthesis problem. Assuming a cost of one for each two-qubit gate, we find all reversible circuits with quantum costs of 4, 5, 6, etc, and give another algorithm to realize these reversible circuits with quantum gates.
BibTeX: @inproceedings{2005_Yangb, author = {Guowu Yang and Hung, W.N.N. and Xiaoyu Song and Perkowski, M.}, title = {Exact synthesis of 3-qubit quantum circuits from non-binary quantum gates using multiple-valued logic and group theory}, journal = {Design, Automation and Test in Europe, 2005. Proceedings}, year = {2005}, pages = { 434 - 435 Vol. 1}, doi = {http://dx.doi.org/10.1109/DATE.2005.145} }
	Proceedings. 34th International Symposium on Multiple-Valued Logic [BibTeX]	2004	Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on , pp. xiv+353	inproceedings	DOI
BibTeX: @inproceedings{2004_,, title = {Proceedings. 34th International Symposium on Multiple-Valued Logic}, journal = {Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on}, year = {2004}, pages = { xiv+353}, doi = {http://dx.doi.org/10.1109/ISMVL.2004.1319903} }
Agrawal, A. & Jha, N.	Synthesis of reversible logic [Abstract] [BibTeX]	2004	Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Vol. 2 , pp. 1384 - 1385 Vol.2	inproceedings	DOI
Abstract: A function is reversible if each input vector produces a unique output vector. Reversible functions find applications in low power design, quantum computing, and nanotechnology. Logic synthesis for reversible circuits differs substantially from traditional logic synthesis. In this paper, we present the first practical synthesis algorithm and tool for reversible functions with a large number of inputs. It uses positive-polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. The heuristic uses a priority queue based search tree and explores candidate factors at each stage in order of attractiveness. The algorithm produces near-optimal results for the examples discussed in the literature. The key contribution of the work is that the heuristic finds very good solutions for reversible functions with a large number of inputs.
BibTeX: @inproceedings{2004_Agrawal, author = {Agrawal, A. and Jha, N.K.}, title = {Synthesis of reversible logic}, journal = {Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings}, year = {2004}, volume = {2}, pages = { 1384 - 1385 Vol.2}, doi = {http://dx.doi.org/10.1109/DATE.2004.1269099} }
Al-Rabadi, A.	Reversible logic neural networks [Abstract] [BibTeX]	2004	Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on Vol. 4 , pp. 2677 - 2682 vol.4	inproceedings	DOI
Abstract: Novel reversible neural network (RevNN) architecture is introduced, and a RevNN paradigm using supervised learning is presented. The application of RevNN to multiple-output feedforward plant control is shown. (k,k) reversible circuits are circuits that have the same number of inputs (k) and outputs (k) and are one-to-one mappings between vectors of inputs and outputs, thus the vector of input values can always be uniquely reconstructed from the vector of output values. Since the reduction of power consumption is a major requirement for the circuit design of future technologies such as in quantum computing, the main features of several future technologies will include reversibility, and thus the new RevNN circuits can play an important role in the design of circuits that consume minimal power for applications such as low-power control of autonomous robots.
BibTeX: @inproceedings{2004_Al-Rabadi, author = {Al-Rabadi, A.N.}, title = {Reversible logic neural networks}, journal = {Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on}, year = {2004}, volume = {4}, pages = { 2677 - 2682 vol.4}, doi = {http://dx.doi.org/10.1109/IJCNN.2004.1381072} }
Al-Rabadi, A.	Reversible fast permutation transforms for quantum circuit synthesis [Abstract] [BibTeX]	2004	Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on , pp. 81 - 86	inproceedings	DOI
Abstract: Multiple-valued quantum circuit synthesis, using permutation-based fast transforms, is introduced. Since the reduction of power consumption is a major requirement for circuit design in future technologies, such as in quantum computing, the main features of several future technologies must include reversibility. Consequently, the new quantum circuits can play an important task in the design of future circuits that consume minimal power.
BibTeX: @inproceedings{2004_Al-Rabadia, author = {Al-Rabadi, A.N.}, title = {Reversible fast permutation transforms for quantum circuit synthesis}, journal = {Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on}, year = {2004}, pages = { 81 - 86}, doi = {http://dx.doi.org/10.1109/ISMVL.2004.1319924} }
Al-Rabadi, A.	Quantum circuit synthesis using classes of GF(3) reversible fast spectral transforms [Abstract] [BibTeX]	2004	Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on , pp. 87 - 93	inproceedings	DOI
Abstract: Novel quantum circuit synthesis, using reversible Davio expansions, is introduced. The new method uses two planes to synthesize the quantum circuits: (1) a reversible butterfly circuit plane; and (2) a plane of quantum gates to perform additions and multiplications. Since the reduction of power consumption is a major requirement for circuit design of future technologies, such as in quantum circuits, the main features of several future technologies must include reversibility, and thus the new synthesis method, using reversible butterfly circuits, can play an important role in the synthesis of circuits that consume minimal power.
BibTeX: @inproceedings{2004_Al-Rabadib, author = {Al-Rabadi, A.N.}, title = {Quantum circuit synthesis using classes of GF(3) reversible fast spectral transforms}, journal = {Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on}, year = {2004}, pages = { 87 - 93}, doi = {http://dx.doi.org/10.1109/ISMVL.2004.1319925} }
Babu, H.; Islam, M.; Chowdhury, S. & Chowdhury, A.	Synthesis of full-adder circuit using reversible logic [Abstract] [BibTeX]	2004	VLSI Design, 2004. Proceedings. 17th International Conference on , pp. 757 - 760	inproceedings	DOI
Abstract: A reversible gate has the equal number of inputs and outputs and one-to-one mappings between input vectors and output vectors; so that, the input vector states can be always uniquely reconstructed from the output vector states. This correspondence introduces a reversible full-adder circuit that requires only three reversible gates and produces least number of "garbage outputs ", that is two. After that, a theorem has been proposed that proves the optimality of the propounded circuit in terms of number of garbage outputs. An efficient algorithm is also introduced in this paper that leads to construct a reversible circuit.
BibTeX: @inproceedings{2004_Babu, author = {Babu, H.M.H. and Islam, M.R. and Chowdhury, S.M.A. and Chowdhury, A.R.}, title = {Synthesis of full-adder circuit using reversible logic}, journal = {VLSI Design, 2004. Proceedings. 17th International Conference on}, year = {2004}, pages = { 757 - 760}, doi = {http://dx.doi.org/10.1109/ICVD.2004.1261020} }
Hayes, J.; Polian, I. & Becker, B.	Testing for missing-gate faults in reversible circuits [Abstract] [BibTeX]	2004	Test Symposium, 2004. 13th Asian , pp. 100 - 105	inproceedings	DOI
Abstract: Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.
BibTeX: @inproceedings{2004_Hayes, author = {Hayes, J.P. and Polian, I. and Becker, B.}, title = {Testing for missing-gate faults in reversible circuits}, journal = {Test Symposium, 2004. 13th Asian}, year = {2004}, pages = { 100 - 105}, doi = {http://dx.doi.org/10.1109/ATS.2004.84} }
Hisakado, T.; Iketo, H. & Okumura, K.	Logically reversible arithmetic circuit using pass-transistor [Abstract] [BibTeX]	2004	Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on Vol. 2 , pp. II - 853-6 Vol.2	inproceedings
Abstract: This paper proposes novel reversible logic circuits, i.e., a reversible ExOR gate and a two-way AND gate. The gates operate in both directions and the input and output are indistinguishable. We design the circuits using dual-line pass-transistor logic. Applying the method to arithmetic circuits, we realize logically reversible arithmetic circuits. Because proposed circuits have no garbage output, the adder and multiplier operate as the subtracter and divider respectively by replacing the input with the output. We confirm the behavior of the circuits by both real experiments and SPICE simulations.
BibTeX: @inproceedings{2004_Hisakado, author = {Hisakado, T. and Iketo, H. and Okumura, K.}, title = {Logically reversible arithmetic circuit using pass-transistor}, journal = {Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on}, year = {2004}, volume = {2}, pages = { II - 853-6 Vol.2} }
Kerntopf, P.	A new heuristic algorithm for reversible logic synthesis [BibTeX]	2004	Design Automation Conference, 2004. Proceedings. 41st , pp. 834 - 837	inproceedings
BibTeX: @inproceedings{2004_Kerntopf, author = {Kerntopf, P.}, title = {A new heuristic algorithm for reversible logic synthesis}, journal = {Design Automation Conference, 2004. Proceedings. 41st}, year = {2004}, pages = { 834 - 837} }
Khan, M.; Perkowski, M. & Khan, M.	Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products] [Abstract] [BibTeX]	2004	Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on , pp. 58 - 67	inproceedings	DOI
Abstract: Ternary Galois field sum of products (TGFSOP) expressions are found to be good choice for ternary reversible, and especially quantum, logic design. In this paper, we propose 16 ternary Galois field expansions (TGFE) and introduce three ternary Galois field decision diagrams (TGFDD) using the proposed TGFEs, which are useful for reversible and quantum logic design. We also propose a heuristic for creating TGFDDs and a method for flattening the TGFDDs for determining TGFSOP expressions. We provide experimental results to show the effectiveness of the developed methods.
BibTeX: @inproceedings{2004_Khan, author = {Khan, M.H.A. and Perkowski, M.A. and Khan, M.R.}, title = {Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products]}, journal = {Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on}, year = {2004}, pages = { 58 - 67}, doi = {http://dx.doi.org/10.1109/ISMVL.2004.1319921} }
Liu, M. & Lent, C.	Bennett and Landauer clocking in quantum-dot cellular automata [Abstract] [BibTeX]	2004	Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on , pp. 120 - 121	inproceedings	DOI
Abstract: Quantum-dot cellular automata (QCA) is a new computation paradigm which encodes bit information by charge configurations. No current flows through the cells; only Coulomb interaction contributes to the computation. Power dissipation has become an important issue in nanotechnology because of the high densities in nano-devices. The chip will melt unless the device dissipates only a small amount of energy to the environment. Landauer (Landauer and Keyes, 1970) has proposed an adiabatic switching method, which has been applied widely in clocked QCA cells (Timler and Lent, 2003). Gradual clocking insures the cells always in the instantaneous ground state, which can provide arbitrarily low power dissipation if the switching process is slow enough. Nondissipative computation can be achieved by keeping a copy to the bits that are going to be erased (Timler and Lent, 2003). Bennett pointed out that any computation could be rendered into reversible format by accumulating a history of all information that would normally thrown away, then disposing this history by the reverse of the process that created it (Bennett, 2000). In this paper, we employ the Bennett clocking design in QCA circuits, which clocks the circuit forward through the cell array and then retreats the clock in a backward sequence. In conventional CMOS considerable overhead in circuit complexity is required to achieve Bennett clocking. In QCA by contrast, no additional circuit complexity is required - only a different clock signal. We show by direct calculation of the equations of motion for a QCA system that energy dissipation less than kBTlog(2) is possible for logically irreversible systems using the Bennett clocking approach.
BibTeX: @inproceedings{2004_Liu, author = {Liu, M. and Lent, C.S.}, title = {Bennett and Landauer clocking in quantum-dot cellular automata}, journal = {Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on}, year = {2004}, pages = { 120 - 121}, doi = {http://dx.doi.org/10.1109/IWCE.2004.1407356} }
Maslov, D. & Dueck, G.	Reversible cascades with minimal garbage [Abstract] [BibTeX]	2004	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 23 (11) , pp. 1497 - 1509	article	DOI
Abstract: The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. We start with the analysis of the number of garbage outputs that must be added to a multiple output function to make it reversible. We give a precise formula for the theoretical minimum of the required number of garbage outputs. For some benchmark functions, we calculate the garbage required by some proposed reversible design methods and compare it to the theoretical minimum. Based on the information about minimal garbage, we suggest a new reversible design method that uses the minimum number of garbage outputs. We show that any Boolean function can be realized as a reversible network in terms of this new approach by giving the theoretical method of finding such a network. Using a heuristics synthesis approach, we create a program and run it to compare results of our synthesis to the previously reported synthesis results for the benchmark functions with up to ten variables. Finally, we show that the synthesis for the proposed model can be accomplished with lower cost than the synthesis of EXOR programmable logic arrays.
BibTeX: @article{2004_Maslov, author = {Maslov, D. and Dueck, G.W.}, title = {Reversible cascades with minimal garbage}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2004}, volume = {23}, number = {11}, pages = { 1497 - 1509}, doi = {http://dx.doi.org/10.1109/TCAD.2004.836735} }
Miller, D.; Dueck, G. & Maslov, D.	A synthesis method for MVL reversible logic [multiple value logic] [Abstract] [BibTeX]	2004	Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on , pp. 74 - 80	inproceedings	DOI
Abstract: An r-valued m-variable reversible logic function maps each of the rm input patterns to a unique output pattern. The synthesis problem is to realize a reversible function by a cascade of primitive reversible gates. In this paper, we present a simple heuristic algorithm that exploits the bidirectional synthesis possibility inherent in the reversibility of the specification. The primitive reversible gates considered here are one possible extension of the well-known binary Toffoli gates. We present exhaustive results for the 9! 2-variable 3-valued reversible functions, comparing the results of our algorithm to optimal results found by breadth-first search. The approach can be applied to general m-variable, r-valued reversible specifications. Further, we show how the presented technique can be applied to irreversible specifications. The synthesis of a 3-input, 3-valued adder is given as a specific case.
BibTeX: @inproceedings{2004_Miller, author = {Miller, D.M. and Dueck, G.W. and Maslov, D.}, title = {A synthesis method for MVL reversible logic [multiple value logic]}, journal = {Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on}, year = {2004}, pages = { 74 - 80}, doi = {http://dx.doi.org/10.1109/ISMVL.2004.1319923} }
Morgan, M. & Bruce, J.	The CRL gateway [Abstract] [BibTeX]	2004	Potentials, IEEE Vol. 22 (5) , pp. 8 - 11	article	DOI
Abstract: Smaller and smaller semiconductor integrated circuits are being designed. Traditional semiconductor fabrication processes are still extremely effective. However, these methods' effectiveness will come to a halt as components shrink to atomic size. Quantum physics then start to govern device behavior. Thus a radical shift, hence upheaval (change is never easy), in computing is a foregone conclusion. But the resulting quantum computers will be tremendously powerful. As our circuits become smaller, the heat they generate becomes harder to control. Much of this heat is a result of the logic function itself, rather than simple resistive dissipation. Therefore, new forms of logic must be considered. Conservative reversible logic (CRL) can reduce the problem of energy dissipated due to logic functions and can be utilized to build quantum computers. Before that can happen, research must be done on how to utilize these gates. Also, a usable synthesis process must be designed. Unparalleled computing power, power savings, and resources are being uncovered. The paper discusses CRL-based gates. They are only models, but models must exist to meet the technology developments required to build quantum computers.
BibTeX: @article{2004_Morgan, author = { Morgan, M. and Bruce, J.W.}, title = {The CRL gateway}, journal = {Potentials, IEEE}, year = {2004}, volume = {22}, number = {5}, pages = { 8 - 11}, doi = {http://dx.doi.org/10.1109/MP.2004.1301238} }
Patel, K.; Hayes, J. & Markov, I.	Fault testing for reversible circuits [Abstract] [BibTeX]	2004	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 23 (8) , pp. 1220 - 1230	article	DOI
Abstract: Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. We consider the test-set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test-set constructions for the standard stuck-at fault model, as well as the usually intractable cell-fault model. We also give a practical test-set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional automatic test pattern generation.
BibTeX: @article{2004_Patel, author = {Patel, K.N. and Hayes, J.P. and Markov, I.L.}, title = {Fault testing for reversible circuits}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2004}, volume = {23}, number = {8}, pages = { 1220 - 1230}, doi = {http://dx.doi.org/10.1109/TCAD.2004.831576} }
Vasudevan, D.; Lala, P. & Parkerson, J.	A novel approach for on-line testable reversible logic circuit design [Abstract] [BibTeX]	2004	Test Symposium, 2004. 13th Asian , pp. 325 -330	inproceedings	DOI
Abstract: Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.
BibTeX: @inproceedings{2004_Vasudevan, author = {D.P. Vasudevan and P.K. Lala and J.P. Parkerson}, title = {A novel approach for on-line testable reversible logic circuit design}, journal = {Test Symposium, 2004. 13th Asian}, year = {2004}, pages = {325 -330}, doi = {http://dx.doi.org/10.1109/ATS.2004.13} }
Vasudevan, D.; Lala, P. & Parkerson, J.	Online testable reversible logic circuit design using NAND blocks [Abstract] [BibTeX]	2004	Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on , pp. 324 - 331	inproceedings	DOI
Abstract: A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.
BibTeX: @inproceedings{2004_Vasudevana, author = {Vasudevan, D.P. and Lala, P.K. and Parkerson, J.P.}, title = {Online testable reversible logic circuit design using NAND blocks}, journal = {Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on}, year = {2004}, pages = { 324 - 331}, doi = {http://dx.doi.org/10.1109/DFTVS.2004.1347856} }
Babu, H.M.H.; Islam, M.R.; Chowdhury, A.R. & Chowdhury, S.M.A.	Reversible logic synthesis for minimization of full-adder circuit [Abstract] [BibTeX]	2003	Digital System Design, 2003. Proceedings. Euromicro Symposium on , pp. 50 - 54	inproceedings	DOI
Abstract: Reversible logic is of the growing importance to many future technologies. A reversible circuit maps each output vector, into a unique input vector, and vice versa. This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the "garbage bit" and number of reversible gates, which is the main challenge of reversible logic synthesis. This proposed full-adder circuit contains only three gates and two garbage outputs whereas earlier full-adder circuit by M. Perkowski et al. (2001) requires four gates and produces two garbage outputs and another existing full-adder circuit by Md. H. H Azad Khan (2002) requires three gates but produces three garbage outputs. Thus, the proposed full-adder circuit is efficient in terms of number of gates with compared to M. Perkowski et al. (2001) as well as in terms of number of garbage outputs with compared to Md. H. H Azad Khan (2002).
BibTeX: @inproceedings{2003_Babu, author = {Hafiz Md Hasan Babu and Md Rafiqul Islam and Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury}, title = {Reversible logic synthesis for minimization of full-adder circuit}, journal = {Digital System Design, 2003. Proceedings. Euromicro Symposium on}, year = {2003}, pages = { 50 - 54}, doi = {http://dx.doi.org/10.1109/DSD.2003.1231899} }
Buller, A. & Perkowski, M.	Evolved reversible cascades realized on the CAM-brain machine [Abstract] [BibTeX]	2003	Evolvable Hardware, 2003. Proceedings. NASA/DoD Conference on , pp. 246 - 251	inproceedings	DOI
Abstract: This paper presents a new approach to reversible cascade evolution based on a 3D cellular automaton. As a research platform we used the ATR's CAMBrain Machine (CBM). Reversible circuits are investigated because they are expected to dissipate much less energy than their irreversible counterparts. One day they will be implemented as nano-scale 3-dimensional chips. A circuit is reversible if the number of its inputs equals the number of its outputs and there is a one-to-one mapping between spaces of input vectors and output vectors. This paper provides: (1) a brief introduction to reversible logic concentrating on definitions and properties of the Feynman, Toffoli, Fredkin gates; (2) an introduction to the 3D cellular logic machine (CLM) that is a cellular automaton with frozen and pulsing state variables; and (3) a collection of reversible structures evolved using a dedicated GA and located in the CBM using the NeuroMaze 3.0 Pro, a software tool for computer-aided design of CBM-style structures.
BibTeX: @inproceedings{2003_Buller, author = {Buller, A. and Perkowski, M.}, title = {Evolved reversible cascades realized on the CAM-brain machine}, journal = {Evolvable Hardware, 2003. Proceedings. NASA/DoD Conference on}, year = {2003}, pages = { 246 - 251}, doi = {http://dx.doi.org/10.1109/EH.2003.1217675} }
Dueck, G.; Maslov, D. & Miller, D.	Transformation-based synthesis of networks of Toffoli/Fredkin gates [Abstract] [BibTeX]	2003	Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on Vol. 1 , pp. 211 - 214 vol.1	inproceedings
Abstract: Reversible logic has attracted significant attention in recent years. It has applications in low power CMOS, quantum computing, nanotechnology, and optical computing. Traditional gates such as AND, OR, and EXOR are not reversible. In fact NOT is the only reversible gate from the traditional set of gates. Several reversible gates have been proposed. Among them are the controlled NOT (also known as the Feynman gate), the Toffoli gate, and the Fredkin gate. An n-input Toffoli gate has n - 1 control lines which pass through the gate unaltered and a target line on which the value is inverted if all the control lines have value '1'. An n-input Fredkin gate has n - 2 control lines which pass through the gate unaltered and two target lines on which the values are swapped if all the control lines have value '1'. A NOT gate is the special case of a Toffoli gate with no control inputs. Likewise, a SWAP gate is the special case of a Fredkin gate with no control inputs. In this paper, we review a transformation-based synthesis procedure targeted to Toffoli gates and show how it can be extended to allow Fredkin gates. This extension results in circuits with fewer gates. The synthesis of reversible logic differs significantly from traditional irreversible logic synthesis approaches. Fan-outs and loops are not permitted due to the target technology. Outputs from one gate are used as inputs to the next gate. This results in a high degree of interdependence among gates. Our algorithm first finds an initial circuit with no backtracking and minimal look-ahead. We exploit reversibility directly in our synthesis approach. This method always finds a solution. Next we apply a set of template transforms that reduce the size of the circuit. We synthesize all three input, three output reversible functions and compare our results to those obtained previously.
BibTeX: @inproceedings{2003_Dueck, author = {Dueck, G.W. and Maslov, D. and Miller, D.M.}, title = {Transformation-based synthesis of networks of Toffoli/Fredkin gates}, journal = {Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on}, year = {2003}, volume = {1}, pages = { 211 - 214 vol.1} }
Maslov, D.; Dueck, G. & Miller, D.	Fredkin/Toffoli templates for reversible logic synthesis [Abstract] [BibTeX]	2003	Computer Aided Design, 2003. ICCAD-2003. International Conference on , pp. 256 - 261	inproceedings
Abstract: Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate and the Fredkin gate. Our synthesis algorithm first finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead. Next we apply transformations that reduce the size of the circuit. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence in the network to be synthesized matches more than half of a template, then a transformation that reduces the gate count can be applied. In this paper we show that Toffoli and Fredkin gates behave in a similar manner. Therefore, some gates in the templates may not need to be specified-they can match a Toffoli or a Fredkin gate. We formalize this by introducing the box gate. All templates with less than six gates are enumerated and classified. We synthesize all three input, three output reversible functions and compare our results to those obtained previously.
BibTeX: @inproceedings{2003_Maslov, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Fredkin/Toffoli templates for reversible logic synthesis}, journal = {Computer Aided Design, 2003. ICCAD-2003. International Conference on}, year = {2003}, pages = { 256 - 261} }
Maslov, D.; Dueck, G. & Miller, D.	Simplification of Toffoli networks via templates [Abstract] [BibTeX]	2003	Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on , pp. 53 - 58	inproceedings
Abstract: Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired junction. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the second step. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence in the network to be synthesized matches more than half of a template, then a transformation reducing the gate count can be applied. All templates for m le;7 are described in this paper.
BibTeX: @inproceedings{2003_Maslova, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Simplification of Toffoli networks via templates}, journal = {Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on}, year = {2003}, pages = { 53 - 58} }
Maslov, D. & Dueck, G.	Improved quantum cost for n-bit Toffoli gates [Abstract] [BibTeX]	2003	Electronics Letters Vol. 39 (25) , pp. 1790 - 1791	article	DOI
Abstract: An n-bit Toffoli gate quantum circuit based on the
BibTeX: @article{2003_Maslovb, author = {Maslov, D. and Dueck, G.W.}, title = {Improved quantum cost for n-bit Toffoli gates}, journal = {Electronics Letters}, year = {2003}, volume = {39}, number = {25}, pages = { 1790 - 1791}, doi = {http://dx.doi.org/10.1049/el:20031202} }
Miller, D.; Maslov, D. & Dueck, G.	A transformation based algorithm for reversible logic synthesis [Abstract] [BibTeX]	2003	Design Automation Conference, 2003. Proceedings , pp. 318 - 323	inproceedings
Abstract: A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing, nanotechnology and low-power CMOS design. Synthesis approaches are not well developed for reversible circuits even for small numbers of inputs and outputs. In this paper, a transformation based algorithm for the synthesis of such a reversible circuit in terms of n times; n Toffoli gates is presented. Initially, a circuit is constructed by a single pass through the specification with minimal look-ahead and no back-tracking. Reduction rules are then applied by simple template matching. The method produces very good results for larger problems.
BibTeX: @inproceedings{2003_Miller, author = {Miller, D.M. and Maslov, D. and Dueck, G.W.}, title = {A transformation based algorithm for reversible logic synthesis}, journal = {Design Automation Conference, 2003. Proceedings}, year = {2003}, pages = { 318 - 323} }
Sasao, T.	Cascade realizations of two-valued input multiple-valued output functions using decomposition of group functions [Abstract] [BibTeX]	2003	Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on , pp. 125 - 132	inproceedings	DOI
Abstract: This paper considers a method to realize a two-valued input three-valued output function f:0, 1n rarr;0, 1, 2 by using a cascade of four-input cells. Decomposition of a group function is used to find a canonical form. We show that the Walsh spectrum specifies the canonical form, and the number of non-zero coefficients in the spectrum is proportional to the number of cells in the cascade. Finally, we show a design algorithm for a p-valued function f:0, 1n rarr;0, 1, ..., p-1. The designed cascades are reversible and conservative.
BibTeX: @inproceedings{2003_Sasao, author = {Sasao, T.}, title = {Cascade realizations of two-valued input multiple-valued output functions using decomposition of group functions}, journal = {Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on}, year = {2003}, pages = { 125 - 132}, doi = {http://dx.doi.org/10.1109/ISMVL.2003.1201396} }
Semenov, V.; Danilov, G. & Averin, D.	Negative-inductance SQUID as the basic element of reversible Josephson-junction circuits [Abstract] [BibTeX]	2003	Applied Superconductivity, IEEE Transactions on Vol. 13 (2) , pp. 938 - 943	article	DOI
Abstract: It has been known for a long time that the thermodynamic limit kBTln2 on the energy dissipation per logic operation can be overcome by physically and logically reversible circuits. However, explicit experimental demonstration of this is still lacking, and would be highly desirable both in its own right and in view of strong interest in inherently reversible quantum computation. In this work, we suggest a new gate, "negative-inductance SQUID", that is suitable for the experimental demonstration of reversible information processing in Josephson-junction circuits, and present results of its theoretical analysis. We also describe layout-level designs of an individual nSQUID and an 8-cell circular shift register made of nSQUIDs.
BibTeX: @article{2003_Semenov, author = {Semenov, V.K. and Danilov, G.V. and Averin, D.V.}, title = {Negative-inductance SQUID as the basic element of reversible Josephson-junction circuits}, journal = {Applied Superconductivity, IEEE Transactions on}, year = {2003}, volume = {13}, number = {2}, pages = { 938 - 943}, doi = {http://dx.doi.org/10.1109/TASC.2003.814155} }
Shende, V.; Prasad, A.; Markov, I. & Hayes, J.	Synthesis of reversible logic circuits [Abstract] [BibTeX]	2003	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 22 (6) , pp. 710 - 722	article	DOI
Abstract: Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics, and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). We prove constructively that every even permutation can be implemented without temporary storage using NOT, CNOT, and TOFFOLI gates. We describe an algorithm for the synthesis of optimal circuits and study the reversible functions on three wires, reporting the distribution of circuit sizes. We also study canonical circuit decompositions where gates of the same kind are grouped together. Finally, in an application important to quantum computing, we synthesize oracle circuits for Grover's search algorithm, and show a significant improvement over a previously proposed synthesis algorithm.
BibTeX: @article{2003_Shende, author = {Shende, V.V. and Prasad, A.K. and Markov, I.L. and Hayes, J.P.}, title = {Synthesis of reversible logic circuits}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2003}, volume = {22}, number = {6}, pages = { 710 - 722}, doi = {http://dx.doi.org/10.1109/TCAD.2003.811448} }
Travaglione, B.	Designing and implementing small quantum circuits and algorithms [Abstract] [BibTeX]	2003	Design Automation Conference, 2003. Proceedings , pp. 894 - 899	inproceedings
Abstract: It appears, in principle, that the laws of quantum mechanics allow a quantum computer to solve certain mathematical problems more rapidly than can be done using a classical computer. However, in order to build such a quantum computer a number of technological problems need to be overcome. A stepping stone to this goal is the implementation of relatively simple quantum algorithms using current experimental techniques. This paper explores small scale quantum algorithms from two different perspectives. Firstly, it shows how small scale quantum algorithms can be tailored to fit current schemes for implementing a quantum computer. Secondly, I review a simple model of computation, based on read-only-memory. This model allows the comparison of the space-efficiency of reversible error-free classical computation with reversible, error-free quantum computation. The quantum model has been shown to be more powerful than the classical model.
BibTeX: @inproceedings{2003_Travaglione, author = {Travaglione, B.}, title = {Designing and implementing small quantum circuits and algorithms}, journal = {Design Automation Conference, 2003. Proceedings}, year = {2003}, pages = { 894 - 899} }
Ziesler, C.; Kim, J.; Papaefthymiou, M. & Kim, S.	Energy recovery design for low-power ASICs [Abstract] [BibTeX]	2003	SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] , pp. 424 - 427	inproceedings	DOI
Abstract: Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV2 rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, exploring VLSI designs that use reversible logic and adiabatic switching to preserve information and achieve nearly zero power dissipation as operating frequencies approach zero. Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. Although their origins can be traced back to the early adiabatic circuits, these so-called energy-recovering systems approach charge recycling from a more practical angle, achieving operating frequencies in the hundreds of MHz with relatively low overhead. Among other energy recovering designs, researchers in the field have demonstrated microcontrollers, standard-cell ASICs, SRAMs, LCD panel drivers, I/O drivers, and multi-GHz clock networks. In this tutorial, we present an overview of the field, focusing on the most promising charge recovering design techniques for ASICs that are close to integration into the field.
BibTeX: @inproceedings{2003_Ziesler, author = {Ziesler, C.H. and Joohee Kim and Papaefthymiou, M.C. and Suhwan Kim}, title = {Energy recovery design for low-power ASICs}, journal = {SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]}, year = {2003}, pages = { 424 - 427}, doi = {http://dx.doi.org/10.1109/SOC.2003.1241561} }
De Vicente, J.; Lanchares, J. & Hermida, R.	FPGA placement by thermodynamic combinatorial optimization [Abstract] [BibTeX]	2002	Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings , pp. 54 -60	inproceedings	DOI
Abstract: In this paper, the placement problem on FPGAs is faced using thermodynamic combinatorial optimization (TCO). TCO is a new combinatorial optimization method based on both thermodynamics and information Theory. In TCO two kinds of processes are considered: microstate and macrostate transformations. Applying the Shannon's definition of entropy to microstate reversible transformations, a probability of acceptance based on Fermi-Dirac statistics is derived On the other hang applying thermodynamic laws to reversible macrostate transformations, an efficient annealing schedule is provided TCO has been compared with simulated annealing (SA) on a set of benchmark circuits for the FPGA placement problem. TCO has achieved large time reductions with respect to SA, while providing interesting adaptive properties
BibTeX: @inproceedings{2002_DeVicente, author = {De Vicente, J. and Lanchares, J. and Hermida, R.}, title = {FPGA placement by thermodynamic combinatorial optimization}, journal = {Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings}, year = {2002}, pages = {54 -60}, doi = {http://dx.doi.org/10.1109/DATE.2002.998249} }
de Garis, H.; Dinerstein, J. & Sriram, R.	A reversible evolvable Boolean network architecture and methodology to overcome the heat generation problem. In molecular scale brain building [Abstract] [BibTeX]	2002	Evolvable Hardware, 2002. Proceedings. NASA/DoD Conference on , pp. 274 - 275	inproceedings	DOI
Abstract: Today's irreversible computing style, in which bits of information are routinely wiped out (e.g. a NAND gate has 2 input bits, and only 1 output bit), cannot continue. If Moore's Law remains valid until 2020, as many commentators think, then the heat generated in molecular scale circuits that Moore's. Law will provide, would be so intense that they will explode (Hall 1992). To avoid such heat generation problems, it has been known since the early 1970s (Bennet 1973) that the secret to "heatless computation" is to compute reversibly, i.e. not to destroy bits, by sending in the input bit-string through a computer built from reversible logic gates (e.g. Fredkin gates [Fredkin et al. 1982]), to record the output answer and then send the output bit-string backwards through the computer to obtain the original input bit-string. This reversible style of computing takes twice as long, but does not destroy bits, hence does not generate heal. (Landauer's principle states that "the heat generated from irreversible computing is derived from the destruction of bits of information" [Landauer 1961]). This paper proposes a reversible evolvable Boolean network architecture and methodology which, it is hoped, will stimulate the evolvable hardware and evolvable neural network research communities to devote more effort towards solving this problem, which can only accentuate as Moore's Law continues to bile.
BibTeX: @inproceedings{2002_Garis, author = {de Garis, H. and Dinerstein, J. and Sriram, R.}, title = {A reversible evolvable Boolean network architecture and methodology to overcome the heat generation problem. In molecular scale brain building}, journal = {Evolvable Hardware, 2002. Proceedings. NASA/DoD Conference on}, year = {2002}, pages = { 274 - 275}, doi = {http://dx.doi.org/10.1109/EH.2002.1029894} }
Kerntopf, P.	Synthesis of multipurpose reversible logic gates [Abstract] [BibTeX]	2002	Digital System Design, 2002. Proceedings. Euromicro Symposium on , pp. 259 - 266	inproceedings	DOI
Abstract: Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose reversible gates are also shown.
BibTeX: @inproceedings{2002_Kerntopf, author = {Kerntopf, P.}, title = {Synthesis of multipurpose reversible logic gates}, journal = {Digital System Design, 2002. Proceedings. Euromicro Symposium on}, year = {2002}, pages = { 259 - 266}, doi = {http://dx.doi.org/10.1109/DSD.2002.1115377} }
Shende, V.; Prasad, A.; Markov, I. & Hayes, J.	Reversible logic circuit synthesis [Abstract] [BibTeX]	2002	Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on , pp. 353 - 360	inproceedings	DOI
Abstract: Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). We prove constructively that every even permutation can be implemented without temporary storage using NOT, CNOT and TOFFOLI gates. We describe an algorithm for the synthesis of optimal circuits and study the reversible functions on three wires, reporting distributions of circuit sizes. Finally, in an application important to quantum computing, we synthesize oracle circuits for Grover's search algorithm, and show a significant improvement over a previously proposed synthesis algorithm.
BibTeX: @inproceedings{2002_Shende, author = {Shende, V.V. and Prasad, A.K. and Markov, I.L. and Hayes, J.P.}, title = {Reversible logic circuit synthesis}, journal = {Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on}, year = {2002}, pages = { 353 - 360}, doi = {http://dx.doi.org/10.1109/ICCAD.2002.1167558} }
Kim, S.; Kwon, J.-H. & Chae, S.-I.	An 8-b nRERL microprocessor for ultra-low-energy applications [Abstract] [BibTeX]	2001	Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific , pp. 27 -28	inproceedings	DOI
Abstract: We describe the design of an nRERL microprocessor for ultra-low-energy applications, nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit using only nMOS transistors, which can be operated at the leakage-current level. We focus on two main issues; first, the design of a full adiabatic microprocessor, which uses only adiabatic components for all the functional blocks, second, the energy consumption of the nRERL microprocessor including its clocked power generator (CPG). With the experimental results, the nRERL microprocessor consumed 26.22 pJ at 440 kHz
BibTeX: @inproceedings{2001_Kim, author = {Seokkee Kim and Jun-Ho Kwon and Soo-Ik Chae}, title = {An 8-b nRERL microprocessor for ultra-low-energy applications}, journal = {Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific}, year = {2001}, pages = {27 -28}, doi = {http://dx.doi.org/10.1109/ASPDAC.2001.913272} }
Park, E.; Tilbury, D. & Khargonekar, P.	A modeling and analysis methodology for modular logic controllers of machining systems using Petri net formalism [Abstract] [BibTeX]	2001	Systems, Man, and Cybernetics, Part C: Applications and Reviews, IEEE Transactions on Vol. 31 (2) , pp. 168 -188	article	DOI
Abstract: Logic controllers for machining systems typically have three control modes: auto, hand and manual. In this paper, a unified formal representation of logic controllers with three control modes is provided using Petri nets (PNs). A modular logic controller structure is introduced and formalized for high-volume transfer lines. The modular logic controller consists of one control module for the mode decision and other control modules for station logic controllers. Each station control module is represented by connecting together operation modules, which are designed with respect to the fault recovery processes of operations; their connection algorithm is also provided. In our formal representation, each control module is represented by a live, safe and reversible PN. A condition for the modular logic controller to generate a correct control logic is provided: the operation causality condition. Using the modular structure of a logic controller, the control logic can be easily reconfigured and automatic code generation is possible
BibTeX: @article{2001_Park, author = {Euisu Park and Tilbury, D.M. and Khargonekar, P.P.}, title = {A modeling and analysis methodology for modular logic controllers of machining systems using Petri net formalism}, journal = {Systems, Man, and Cybernetics, Part C: Applications and Reviews, IEEE Transactions on}, year = {2001}, volume = {31}, number = {2}, pages = {168 -188}, doi = {http://dx.doi.org/10.1109/5326.941841} }
Perkowski, M.; Kerntopf, P.; Buller, A.; Chrzanowska-Jeske, M.; Mishchenko, A.; Song, X.; Al-Rabadi, A.; Jezwiak, L.; Coppola, A. & Massey, B.	Regular realization of symmetric functions using reversible logic [Abstract] [BibTeX]	2001	Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on , pp. 245 -252	inproceedings	DOI
Abstract: Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2*2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little ldquo;garbage rdquo;. Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can also be used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs
BibTeX: @inproceedings{2001_Perkowski, author = {Perkowski, M. and Kerntopf, P. and Buller, A. and Chrzanowska-Jeske, M. and Mishchenko, A. and Xiaoyu Song and Al-Rabadi, A. and Jezwiak, L. and Coppola, A. and Massey, B.}, title = {Regular realization of symmetric functions using reversible logic }, journal = {Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on}, year = {2001}, pages = {245 -252}, doi = {http://dx.doi.org/10.1109/DSD.2001.952289} }
Kwon, J.-H.; Lim, J. & Chae, S.-I.	A three-port nRERL register file for ultra-low-energy applications [Abstract] [BibTeX]	2000	Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on , pp. 161 - 166	inproceedings
Abstract: In this paper, we propose an adiabatic register file for ultra-low-energy applications, which uses a new reversible adiabatic logic, nRERL. The nRERL register file discards garbage information with minimal energy dissipation. We designed a 16 times;8b three-port nRERL register file. From SPICE simulations, we found that the nRERL register file consumes less than 10% of the energy consumed in the conventional register file at a frequency of lower than 1 MHz. We also describe how to design a RAM, a large array of storage cells.
BibTeX: @inproceedings{2000_Kwon, author = {Jun-Ho Kwon and Joonho Lim and Soo-Ik Chae}, title = {A three-port nRERL register file for ultra-low-energy applications}, journal = {Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on}, year = {2000}, pages = { 161 - 166} }
Lim, J.; Kim, D.-G.; Kang, S.-C. & Chae, S.-I.	An 8 times;8-b nRERL serial multiplier for ultra-low-power applications [Abstract] [BibTeX]	2000	Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific , pp. 35 -36	inproceedings	DOI
Abstract: An 8 times;8-b nRERL serial multiplier is implemented in a 0.6- mu;m n-well 3-metal CMOS process. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current level for ultra-low-energy applications. Measurement results showed that the nRERL serial multiplier consumed only 0.9% of the energy dissipation by the static CMOS type at the operating frequency 100 kHz at 5 V, where its adiabatic and leakage losses were about equal
BibTeX: @inproceedings{2000_Lim, author = {Joonho Lim and Dong-Gyu Kim and Sang-Chul Kang and Soo-Ik Chae}, title = {An 8 times;8-b nRERL serial multiplier for ultra-low-power applications}, journal = {Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific}, year = {2000}, pages = {35 -36}, doi = {http://dx.doi.org/10.1109/ASPDAC.2000.835066} }
Mange, D.; Sipper, M.; Stauffer, A. & Tempesti, G.	Toward robust integrated circuits: The embryonics approach [Abstract] [BibTeX]	2000	Proceedings of the IEEE Vol. 88 (4) , pp. 516 -543	article	DOI
Abstract: The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. The Embryonics architecture is based on four hierarchical levels of organization. (1) The basic primitive of our system is the molecule, a multiplexer-based element of a novel programmable circuit. (2) A finite set of molecules makes up a cell, essentially a small processor with an associated memory. (3) A finite set of cells makes up an organism, an application-specific multiprocessor system. (4) The organism can itself replicate, giving rise to a population of identical organisms. We begin by describing in detail the implementation of an artificial cell characterized by a fixed architecture, showing that multicellular arrays can realize a variety of different organisms, all capable of self-replication and self-repair. In order to allow for a wide range of applications, we then introduce a flexible architecture, realized using a new type of fine-grained field-programmable gate array whose basic element, our molecule, is essentially a programmable multiplexer. We describe the implementation of such a molecule, with built-in self-test, and illustrate its use in realizing two applications: a modulo-4 reversible counter (a unicellular organism) and a timer ( a complex multicellular organism). We describe our ongoing research efforts to meet three challenges: a scientific challenge, that of implementing the original specifications formulated by John von Neumann for the conception of a self-replicating automaton; a technical challenge, that of realizing very robust integrated circuits capable of self-repair and self-replication; and a biological challenge, that of attempting to show that the microscopic architectures of artificial and natural organisms, i.e., their genomes, share common properties
BibTeX: @article{2000_Mange, author = {Mange, D. and Sipper, M. and Stauffer, A. and Tempesti, G.}, title = {Toward robust integrated circuits: The embryonics approach}, journal = {Proceedings of the IEEE}, year = {2000}, volume = {88}, number = {4}, pages = {516 -543}, doi = {http://dx.doi.org/10.1109/5.842998} }
Park, E.; Tilbury, D. & Khargonekar, P.	A modeling and analysis methodology for modular logic controllers of machining systems with auto, hand, and manual control modes [Abstract] [BibTeX]	2000	American Control Conference, 2000. Proceedings of the 2000 Vol. 5 , pp. 3158 -3164 vol.5	inproceedings	DOI
Abstract: Logic controllers for machining systems typically have three control modes: auto, hand, and manual. Hand and manual modes are designed for various fault recovery operations in machining systems. In this paper, a unified formal representation of logic controllers with three control modes is provided using Petri nets. A modular logic controller structure is introduced and formalized for reconfigurable high-volume transfer lines. The modular logic controller consists of a control module for mode decision and control modules for station logic controllers. Each station control module is represented by connecting operation modules which are designed with respect to the fault recovery processes of operations; their connection algorithm is also provided. In our formal representation, each control module is represented by a live, safe, and reversible Petri net. A condition for the modular logic controller to generate a correct control logic is provided
BibTeX: @inproceedings{2000_Park, author = {Euisu Park and Tilbury, D.M. and Khargonekar, P.P.}, title = {A modeling and analysis methodology for modular logic controllers of machining systems with auto, hand, and manual control modes}, journal = {American Control Conference, 2000. Proceedings of the 2000}, year = {2000}, volume = {5}, pages = {3158 -3164 vol.5}, doi = {http://dx.doi.org/10.1109/ACC.2000.879147} }
Klein, J.; Leete, T. & Rubin, H.	A biomolecular implementation of logically reversible computation with minimal energy dissipation [Abstract] [BibTeX]	1999	Evolutionary Computation, 1999. CEC 99. Proceedings of the 1999 Congress on Vol. 2 , pp. 1005 Vol. 2	inproceedings	DOI
Abstract: Energy dissipation associated with logic operations imposes a fundamental physical limit on computation and is generated by the entropic cost of information erasure, which is a consequence of irreversible logic elements. We show how to encode information in DNA and use DNA amplification to implement a logically reversible gate that comprises a complete set of operators capable of universal computation. We also propose a method using this design to connect, or `wire', these gates together in a biochemical fashion to create a logic network, allowing complex parallel computations to be executed. The architecture of the system permits highly parallel operations and has properties that resemble well known genetic regulatory systems
BibTeX: @inproceedings{1999_Klein, author = {Klein, J.P. and Leete, T.H. and Rubin, H.}, title = {A biomolecular implementation of logically reversible computation with minimal energy dissipation}, journal = {Evolutionary Computation, 1999. CEC 99. Proceedings of the 1999 Congress on}, year = {1999}, volume = {2}, pages = {1005 Vol. 2}, doi = {http://dx.doi.org/10.1109/CEC.1999.782532} }
Lim, J.; Kim, D.-G. & Chae, S.-I.	A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems [Abstract] [BibTeX]	1999	Solid-State Circuits, IEEE Journal of Vol. 34 (6) , pp. 898 -903	article	DOI
Abstract: In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 mu;m CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal
BibTeX: @article{1999_Lim, author = {Joonho Lim and Dong-Gyu Kim and Soo-Ik Chae}, title = {A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems}, journal = {Solid-State Circuits, IEEE Journal of}, year = {1999}, volume = {34}, number = {6}, pages = {898 -903}, doi = {http://dx.doi.org/10.1109/4.766827} }
Lolas, C.; Soudris, D.; Karafyllidis, I. & Thanailakis, A.	A new adiabatic technique for designing low power array architectures [Abstract] [BibTeX]	1999	Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on Vol. 2 , pp. 795 -798 vol.2	inproceedings	DOI
Abstract: A new approach for implementing low power array architectures based on energy recovery techniques (i.e. adiabatic switching) is introduced. The main principles of the reversible pipeline are adopted. However, its large hardware complexity does not allow efficient implementations. Exploiting the inherent property of a reversible pipeline system that the ldquo;reverse rdquo; logic blocks are used in different time instances and the characteristic that several applications have identical logic blocks, we can reduce the hardware complexity significantly. Here, emphasis is given to the hardware reduction and function of the proposed reversible pipeline architectures. Using an appropriate multiplexer and clocking strategy, we can achieve the reversible operation with small hardware cost. The proposed approach is suitable for implementing array processor architectures, which realize a certain class of Digital Signal Processing (DSP) applications
BibTeX: @inproceedings{1999_Lolas, author = {Lolas, C.Z. and Soudris, D. and Karafyllidis, I. and Thanailakis, A.}, title = {A new adiabatic technique for designing low power array architectures}, journal = {Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on}, year = {1999}, volume = {2}, pages = {795 -798 vol.2}, doi = {http://dx.doi.org/10.1109/ICECS.1999.813228} }
Jung, K. & Kim, W.	A logic gate for reversible pipelining [Abstract] [BibTeX]	1997	Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on Vol. 3 , pp. 1928 -1931 vol.3	inproceedings	DOI
Abstract: This paper describes a logic gate for reversible pipelining that needs about 2 times;(number of input signals) of transistors and 4-phase clock, which is approximately half of those of other circuits either in transistor count or in clock phase. Simulation results of a 2-stage shift register based on this gate show that this implementation with a clock generator dissipates 59% less power than the theoretical power dissipation lower limit of conventional CMOS implementations
BibTeX: @inproceedings{1997_Jung, author = {Keewook Jung and Wonchan Kim}, title = {A logic gate for reversible pipelining}, journal = {Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on}, year = {1997}, volume = {3}, pages = {1928 -1931 vol.3}, doi = {http://dx.doi.org/10.1109/ISCAS.1997.621528} }
De, V. & Meindl, J.	Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration [Abstract] [BibTeX]	1996	Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International , pp. 298 -299, 461	inproceedings	DOI
Abstract: A fundamental opportunity for adiabatic-reversible computation is prescribed by the second law of thermodynamics through the universal relationship between entropy and heat generation in a closed system. The complementary adiabatic MOS (CAMOS) and fully adiabatic MOS (ADMOS) logic families provide practical circuit implementations of quasi-adiabatic and quasi-adiabatic-reversible computing, respectively, and offer promising alternatives to CMOS logic for low-power GSI systems
BibTeX: @inproceedings{1996_De, author = {De, V.K. and Meindl, J.D.}, title = {Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration}, journal = {Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International}, year = {1996}, pages = {298 -299, 461}, doi = {http://dx.doi.org/10.1109/ISSCC.1996.488626} }
Ip, C. & Dill, D.	State reduction using reversible rules [Abstract] [BibTeX]	1996	Design Automation Conference Proceedings 1996, 33rd , pp. 564 -567	inproceedings
Abstract: We reduce the state explosion problem in automatic verification of finite-state systems by automatically collapsing subgraphs of the state graph into abstract states. The key idea of the method is to identify state generation rules that can be inverted. It can be used for verification of deadlock-freedom, error and invariant checking and stuttering-invariant CTL model checking
BibTeX: @inproceedings{1996_Ip, author = {Ip, C.N. and Dill, D.L.}, title = {State reduction using reversible rules}, journal = {Design Automation Conference Proceedings 1996, 33rd}, year = {1996}, pages = {564 -567} }
Powell, J.; Trezza, J.; Morf, M. & Harris, J.	Vertical cavity X-modulators for reconfigurable optical interconnection and routing [Abstract] [BibTeX]	1996	Massively Parallel Processing Using Optical Interconnections, 1996., Proceedings of the Third International Conference on , pp. 352 -359	inproceedings	DOI
Abstract: We are continuing to develop conservative and reversible optoelectronic intensity modulators. In our first device, two of the inputs are optical and the third in the device's initial implementation is an electrical control signal. These devices are essentially controllable optical routing elements, or controllable mirrors or beam-splitters. In one state beams incident from opposite sides of the device are reflected and in the other state they are transmitted. Using arrays of these devices, various switching networks can be constructed including crossbar switches and other regular or irregular 2- or 3-D architectures. The device structure is composed of quantum wells in a Fabry-Perot cavity. Our devices are grown using molecular beam epitaxy (MBE) using the InGaAs materials system with in-situ reflectivity measurements and subsequent growth corrections. The design of the devices or arrays of devices can be focused on optimizing bandwidth, modulation ratio, voltage, or change in reflectivity, depending on the denied application. Several systems applications and associated device refinements are discussed
BibTeX: @inproceedings{1996_Powell, author = {Powell, J.S. and Trezza, J.A. and Morf, M. and Harris, J.S.}, title = {Vertical cavity X-modulators for reconfigurable optical interconnection and routing}, journal = {Massively Parallel Processing Using Optical Interconnections, 1996., Proceedings of the Third International Conference on}, year = {1996}, pages = {352 -359}, doi = {http://dx.doi.org/10.1109/MPPOI.1996.559120} }
Ye, Y. & Roy, K.	Energy recovery circuits using reversible and partially reversible logic [Abstract] [BibTeX]	1996	Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Vol. 43 (9) , pp. 769 -778	article	DOI
Abstract: This paper presents a new family of logic gates for low energy computing using pulsed power CMOS logic. The logic gates use the principles of adiabatic-switching and results show that in typical cases 90% of the energy can be recovered with operating frequency around 1 MHz. Constant capacitance condition is enforced in our designs so that signals' energy can be efficiently recycled in the chip. We also present a detailed analysis and modeling of energy dissipation in adiabatic circuits. The models were experimentally validated using the circuit simulator SPICE. A simplified version of adiabatic logic with simplicity comparable to static CMOS circuits is also presented. For a 2 times;2 multiplier using this type of logic, 60% of energy can be saved over static CMOS case at 20 MHz and there is 35% less energy consumption at 100 MHz
BibTeX: @article{1996_Ye, author = {Yibin Ye and Roy, K.}, title = {Energy recovery circuits using reversible and partially reversible logic}, journal = {Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on}, year = {1996}, volume = {43}, number = {9}, pages = {769 -778}, doi = {http://dx.doi.org/10.1109/81.536746} }
Athas, W. & Svensson, L.	Reversible logic issues in adiabatic CMOS [Abstract] [BibTeX]	1994	Physics and Computation, 1994. PhysComp '94, Proceedings., Workshop on , pp. 111 -118	inproceedings	DOI
Abstract: Power dissipation in CMOS circuits has become increasingly important for the design of portable, embedded and high-performance computing systems. Our VLSI research group has investigated a novel form of energy-conserving logic suitable for CMOS. Through small chip-building experiments, we have demonstrated the low-power operation of simple logic functions. These chips have used logical reversibility on a small, sometimes trivial, scale to achieve their low-power operation. In moving towards more complex functions, the role of reversibility will increase. This paper addresses two problem areas that we have found to be crucial to successfully realizing low-power operation of CMOS chips using reversible logic techniques. The first area is the energy-efficient design of the combined power supply and clock generator. The second is the logical overhead needed to support reversible logic functions. The first problem area, though formidable, seems amenable to systematic approaches. Significant inroads have been made towards finding practical, efficient solutions. The second, however, appears to be by far the more difficult hurdle to overcome irreversible logic is to become an attractive approach for reducing power dissipation in CMOS
BibTeX: @inproceedings{1994_Athas, author = {Athas, W.C. and Svensson, L.J.}, title = {Reversible logic issues in adiabatic CMOS}, journal = {Physics and Computation, 1994. PhysComp '94, Proceedings., Workshop on}, year = {1994}, pages = {111 -118}, doi = {http://dx.doi.org/10.1109/PHYCMP.1994.363692} }
DiVincenzo, D. & Smolin, J.	Results on two-bit gate design for quantum computers [Abstract] [BibTeX]	1994	Physics and Computation, 1994. PhysComp '94, Proceedings., Workshop on , pp. 14 -23	inproceedings	DOI
Abstract: We present numerical results which show how two-bit logic gates can be used in the design of a quantum computer. We show that the Toffoli gate, which is the universal gate for all classical reversible computation, can be implemented using a particular sequence of exactly five two-bit gates. An arbitrary three-bit unitary gate, which can be used to build up any arbitrary quantum computation, can be implemented exactly with six two-bit gates. The ease of implementation of any particular quantum operation is dependent upon a very nonclassical feature of the operation, its exact quantum phase factor
BibTeX: @inproceedings{1994_DiVincenzo, author = {DiVincenzo, D.P. and Smolin, J.}, title = {Results on two-bit gate design for quantum computers}, journal = {Physics and Computation, 1994. PhysComp '94, Proceedings., Workshop on}, year = {1994}, pages = {14 -23}, doi = {http://dx.doi.org/10.1109/PHYCMP.1994.363704} }
Storrs Hall, J.	A reversible instruction set architecture and algorithms [Abstract] [BibTeX]	1994	Physics and Computation, 1994. PhysComp '94, Proceedings., Workshop on , pp. 128 -134	inproceedings	DOI
Abstract: We describe a reversible instruction set architecture using recently developed reversible logic design techniques. Such an architecture has the dual advantage of being able to run backwards and of being, in theory, implementable so as to dissipate less than log 2 kT joules per bit operation. We analyze several basic control structures and algorithms on the architecture, showing that, for example, a sorting algorithm need only dissipate O(n log n) bits even though it makes O(n 2) comparisons
BibTeX: @inproceedings{1994_StorrsHall, author = {Storrs Hall, J.}, title = {A reversible instruction set architecture and algorithms}, journal = {Physics and Computation, 1994. PhysComp '94, Proceedings., Workshop on}, year = {1994}, pages = {128 -134}, doi = {http://dx.doi.org/10.1109/PHYCMP.1994.363690} }
Kaplunenko, V.; Khabipov, M.; Khokhlov, D.; Kirichenko, A.; Koshelets, V. & Kovtonyuk, S.	Experimental implementation of SFQ NDRO cells and 8-bit ADC [Abstract] [BibTeX]	1993	Applied Superconductivity, IEEE Transactions on Vol. 3 (1) , pp. 2662 -2665	article	DOI
Abstract: Two single-flux quantum (SFQ) logic elements have been designed, fabricated, and successfully tested: an 8 b analog-to-digital converter (ADC) and nondestructive readout (NDRO) cells. The converter consists of an input coil, a comparator, and a reversible ripple counter. The ADC shows a good linearity ( plusmn;12 mA) and a quite high calculated frequency range (up to 2.5 GHz). Two types of input coils differing in inductance and two types of NDRO units also have been investigated: with direct and magnetic coupling between interferometers. The integrated circuits are fabricated using 4 mu;m Nb-AlOx-Nb trilayer technology with a critical current density of about 1000 A/cm. This techniques makes it possible to produce NDRO cells operating up to 10 GHz frequency
BibTeX: @article{1993_Kaplunenko, author = {Kaplunenko, V.K. and Khabipov, M.I. and Khokhlov, D.Yu. and Kirichenko, A.F. and Koshelets, V.P. and Kovtonyuk, S.A.}, title = {Experimental implementation of SFQ NDRO cells and 8-bit ADC}, journal = {Applied Superconductivity, IEEE Transactions on}, year = {1993}, volume = {3}, number = {1}, pages = {2662 -2665}, doi = {http://dx.doi.org/10.1109/77.233975} }
Jennings, G.	Reversible functional simulation for digital system design [Abstract] [BibTeX]	1991	Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991 , pp. 8.2/1 -8.2/4	inproceedings	DOI
Abstract: A simulation method which allows the simulator to backtrack, to fully reproduce its configuration from earlier cycles, greatly assists debugging of complex synchronous digital systems. The author describes the principles of this simulator, briefly discusses static schedules and how they drive the component models, and shows the modifications (including those to the latch model) which allow reversible simulation. He then shows how the schedules and components coordinate to run either forward or in reverse. This is done for a two-phase clocking discipline, and can easily be adapted to single clock modeling
BibTeX: @inproceedings{1991_Jennings, author = {Jennings, G.}, title = {Reversible functional simulation for digital system design}, journal = {Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991}, year = {1991}, pages = {8.2/1 -8.2/4}, doi = {http://dx.doi.org/10.1109/CICC.1991.163991} }
Likharev, K.; Rylov, S. & Semenov, V.	Reversible conveyer computation in array of parametric quantrons [Abstract] [BibTeX]	1985	Magnetics, IEEE Transactions on Vol. 21 (2) , pp. 947 - 950	article
Abstract: A possibility of physically and logically reversible processing of digital information in Josephson-junction circuits of a reasonable complexity has been considered. As example, a 8-bit 1024-point fast convolver has been designed on the basis of a two-dimentional quasi-uniform array ofsim 250times30,000parametric quantrons. This completely reversible conveyer device can operate with the estimated rate of at leastsim10^9numbers per second, which corresponds tosim10^14binary logical operations per second. At this rate the power dissipation in the whole device can still be as low as #8764;30nW. A new mode of the parametric quantron operation with larger parameter margins is also described.
BibTeX: @article{1985_Likharev, author = { Likharev, K. and Rylov, S. and Semenov, V.}, title = {Reversible conveyer computation in array of parametric quantrons}, journal = {Magnetics, IEEE Transactions on}, year = {1985}, volume = {21}, number = {2}, pages = { 947 - 950} }
Cova, S.; Dotti, D. & Tenconi, S.M.	Automated Digital Measurements of CV Curves and Derivatives, and of Capacitance Transients for Semiconductor Evaluation [Abstract] [BibTeX]	1973	Instrumentation and Measurement, IEEE Transactions on Vol. 22 (4) , pp. 347 -355	article	DOI
Abstract: A system of instruments is presented for automated digital measurements of voltage and/or time dependent capacitances. The system has been designed for the evaluation of semiconductor materials and devices. It is based on a fast capacitance-inverse-to-frequency converter (FCFC), where a direct conversion is obtained with high accuracy, and where the device to be tested can be subject to dc, modulated, and pulsed voltage bias. The output frequency (of the order of 1 MHz) accurately foliows capacitance variations, even if occurring in short times (less than 100 Ms). Biasing circuits, a multichannel scaler, and logic interface circuits complete the system. Stationary and nonstationary CV curves and time variations of capacitances can be accuratety measured. The precision can be improved by averagng over many repetitions of the measurement. Derivatives (first and higher orders) of CV curves can also be directly and accurately measured by using a technique based on voltage modulation and synchronous reversible counting. This feature also makes it possible to obtain accurate measurements of doping profiles in semiconductors. Representative experimental results obtained with the system are shown.
BibTeX: @article{1973_Cova, author = {Cova, Sergio and Dotti, Domenico and Tenconi, Sandro M.}, title = {Automated Digital Measurements of CV Curves and Derivatives, and of Capacitance Transients for Semiconductor Evaluation}, journal = {Instrumentation and Measurement, IEEE Transactions on}, year = {1973}, volume = {22}, number = {4}, pages = {347 -355}, doi = {http://dx.doi.org/10.1109/TIM.1973.4314186} }
Gaertner, W.W.	Adaptable Large-Scale-Integrated Military and Space Systems [Abstract] [BibTeX]	1966	Aerospace and Electronic Systems, IEEE Transactions on Vol. AES-2 (6-Suppl) , pp. 135 -141	article	DOI
Abstract: The advent of low-cost microelectronics and of large-scale integration (LSI) in particular has made it practical to design adaptable circuits and systems to achieve various significant objectives. The two objectives discussed in this paper are the design and technology of Microelectronic Multifunction Circuit Blocks to specifically simplify the logistics support problem of large, long-life military systems and the use of Dynamically Redundant Microelectronic Circuit Blocks to mechanize efficient self-repair systems. Presently practical adaptation techniques involve reversible and irresversible electronic modification of the interconnection pattern which is super-imposed on a matrix of components or of logic or analog circuits. Future possibilities include changes in the component characteristics themselves. Among the various design and technological approaches to adaptable multifunction microcircuits the Pin-Programmable Adaptable Microcircuits are recognized as the most versatile. This adaptation scheme is then extended to include dynamically redundant microcircuits. The basic principle of dynamic redundancy is that the interconnection paths between the redundant circuit blocks are not fixed but can be varied by external control signals. This adaptation is accomplished by switches placed around distribution points in the interconnection pattern. The switches are opened and closed by a logic control network programmed by an Equipment Redundacny Programme. Each circuit can operate in various Redundancy Modes depending on the state of the switches around it. The basic terms are defined and the advantages of dynamic redundancy are listed.
BibTeX: @article{1966_Gaertner, author = {Gaertner, W. W.}, title = {Adaptable Large-Scale-Integrated Military and Space Systems}, journal = {Aerospace and Electronic Systems, IEEE Transactions on}, year = {1966}, volume = {AES-2}, number = {6-Suppl}, pages = {135 -141}, doi = {http://dx.doi.org/10.1109/TAES.1966.4502002} }
Duff, D.L. & Ludbrook, A.	Reversing Thyristor Armature Dual Converter with Logic Crossover Control [Abstract] [BibTeX]	1965	Industry and General Applications, IEEE Transactions on Vol. IGA-1 (3) , pp. 216 -222	article	DOI
Abstract: Several techniques are available for the design of reversible armature power supplies. The approach described in this paper results in a very high performance system and retains the high conversion efficiency of a single converter bridge. A unique firing circuit and regulator design allows the transfer characteristics of the two converter bridges to be coincident. Logic circuitry is used to select the operating bridge dependent on system requirements Performance characteristics are discussed with particular reference to test results obtained from a 100-hp reversing screw-down supply.
BibTeX: @article{1965_Duff, author = {Duff, David L. and Ludbrook, Allan}, title = {Reversing Thyristor Armature Dual Converter with Logic Crossover Control}, journal = {Industry and General Applications, IEEE Transactions on}, year = {1965}, volume = {IGA-1}, number = {3}, pages = {216 -222}, doi = {http://dx.doi.org/10.1109/TIGA.1965.4180544} }
Loev, D.; Miehle, W.; Paivinen, J. & Wylen, J.	Magnetic Core Circuits for Digital Data-Processing Systems [Abstract] [BibTeX]	1956	Proceedings of the IRE Vol. 44 (2) , pp. 154 -162	article	DOI
Abstract: A magnetic core has a switching time of a few microseconds and has the ability to store binary information indefinitely without application of power. New techniques for using cores in digital data-processing systems are described. Reference is made to a system containing eight hundred cores to indicate reliability, and size and power requirements relative to a vacuum tube version. Three fundamental interconnecting circuits for data transfer are described. These are the single-diode loop, and a new split winding loop, and new inhibit loop. The single-diode loop permits unconditional transfer of information from one or more transmitting cores to one or more receiving cores. The split-winding loop allows conditional transfer between cores and thus permits logical operations upon isolated cores. The inhibit loop offers a reliable method for conditionally inhibiting the transfer of information from one core to another. A logical symbolism for these loops has been found useful in system design and analysis. Units performing the functions of storage, control, and logic are explained. These are shift registers (serial, parallel, and reversible); cycle distributors and counters; negation, inclusive- or, conjunction, exclusive- or, and material equivalence (compare). System design considerations are illustrated by two examples of half-adders.
BibTeX: @article{1956_Loev, author = {Loev, D. and Miehle, W. and Paivinen, J. and Wylen, J.}, title = {Magnetic Core Circuits for Digital Data-Processing Systems}, journal = {Proceedings of the IRE}, year = {1956}, volume = {44}, number = {2}, pages = {154 -162}, doi = {http://dx.doi.org/10.1109/JRPROC.1956.274899} }

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