Mise à jour du 13 mars 2010

Research Pages

Reversible Computer

Titres

Copy of the Micropower Project
by Dr. Robert Glück et al.

Reversible Computing by
Pr. Alexis De Vos

The Reversible and Quantum
Computing Research Group
University of FLORIDA

Bibliography
by Stéphane BURIGNAT

Video Encoding

Reversible Circuits Synthesis

Reversible Logic Design

Bibliography on Synthesis of Reversible circuits - Table

JabRef References output

Author / Editor / Organization	Title	Year	Journal / Proceedings / Book	BibTeX type	DOI/URL
Arabzadeh, M.; Saeedi, M. & Zamani, M.S.	Rule-based optimization of reversible circuits [Abstract] [BibTeX]	2010	Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific , pp. 849 -854	inproceedings	DOI
Abstract: Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed. To evaluate the proposed approach, the best-reported synthesized circuits and the results of a recent synthesis algorithm which uses both negative and positive controls are used. Our experiments reveal the potential of the proposed approach in optimizing synthesized circuits.
BibTeX: @inproceedings{2010_Arabzadeh, author = {Arabzadeh, Mona and Saeedi, Mehdi and Zamani, Morteza Saheb}, title = {Rule-based optimization of reversible circuits}, journal = {Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific}, year = {2010}, pages = {849 -854}, doi = {http://dx.doi.org/10.1109/ASPDAC.2010.5419685} }
Arabzadeh, M.; Saeedi, M. & Zamani, M.S.	Rule-based optimization of reversible circuits [Abstract] [BibTeX]	2010	Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific , pp. 849 -854	inproceedings	DOI
Abstract: Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed. To evaluate the proposed approach, the best-reported synthesized circuits and the results of a recent synthesis algorithm which uses both negative and positive controls are used. Our experiments reveal the potential of the proposed approach in optimizing synthesized circuits.
BibTeX: @inproceedings{2010_Arabzadeha, author = {Arabzadeh, Mona and Saeedi, Mehdi and Zamani, Morteza Saheb}, title = {Rule-based optimization of reversible circuits}, journal = {Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific}, year = {2010}, pages = {849 -854}, doi = {http://dx.doi.org/10.1109/ASPDAC.2010.5419684} }
Hashmi, I. & Babu, H.	An Efficient Design of a Reversible Barrel Shifter [Abstract] [BibTeX]	2010	VLSI Design, 2010. VLSID '10. 23rd International Conference on , pp. 93 -98	inproceedings	DOI
Abstract: The key objective of today's circuit design is to increase the performance without the proportional increase in power consumption. In this regard, reversible logic has become an immensely promising technology in the field of low power computing and designing. On the other hand, data shifting and rotating are required in many operations such as arithmetic and logical operations, address decoding and indexing etc. In this consequence, barrel shifters, which can shift and rotate multiple bits in a single cycle, have become a common design choice for high speed applications. For this reason, this paper presents an efficient design of a reversible barrel shifter. It has also been shown that the new circuit outperforms the previously proposed one in terms of number of gates, number of garbage outputs, delay and quantum cost.
BibTeX: @inproceedings{2010_Hashmi, author = {Hashmi, I. and Babu, H.M.H.}, title = {An Efficient Design of a Reversible Barrel Shifter}, journal = {VLSI Design, 2010. VLSID '10. 23rd International Conference on}, year = {2010}, pages = {93 -98}, doi = {http://dx.doi.org/10.1109/VLSI.Design.2010.35} }
Khalil, A.S.G.; Hartner, S.; Ali, M.; Gupta, A.; Wiggers, H. & Winterer, M.	Stable aqueous dispersions of ZnO nanoparticles for ink-jet printed gas sensors [Abstract] [BibTeX]	2010	Nanoelectronics Conference (INEC), 2010 3rd International , pp. 440 -441	inproceedings	DOI
Abstract: For the preparation of printable devices based on ZnO nanoparticles (ZnO NP), stable colloidal dispersions of these materials are highly desirable. ZnO NP have been synthesized by Chemical Vapor Synthesis. The particles have a spherical shape with a narrow size distribution. Stable aqueous dispersions of the ZnO NP have been successfully prepared after the addition of a polymeric stabilizer. The prepared dispersions are stable for at least 2 months without observable sedimentation. These stable dispersions are used to prepare ZnO NP films on different substrates by ink-jet printing. The viscosity and the surface tension of the dispersion as well as the printing parameters have been optimized for forming layers with high quality. Dense and low porosity layers of ZnO NP with a thickness between 100 #x2013;250 nm have been prepared on different substrates. First measurements on ink-jet printed ZnO films are done on self fabricated inter digital capacitors (IDCs) at room temperature. The ZnO films show resistivity at room temperature of 7.76 k #x2126;.cm. For sensing measurements in hydrogen atmosphere, the sheet resistance decreases rapidly until it reaching metallic behavior. This behavior is reversible.
BibTeX: @inproceedings{2010_Khalil, author = {Khalil, Ahmed S. G. and Hartner, Sonja and Ali, Moazzam and Gupta, Anoop and Wiggers, Hartmut and Winterer, Markus}, title = {Stable aqueous dispersions of ZnO nanoparticles for ink-jet printed gas sensors}, journal = {Nanoelectronics Conference (INEC), 2010 3rd International}, year = {2010}, pages = {440 -441}, doi = {http://dx.doi.org/10.1109/INEC.2010.5424503} }
Qiu, Y.; Chen, W. & Yang, S.	Synthesis and high lithium electroactivity of rutile TiO2@C nanorods [Abstract] [BibTeX]	2010	Nanoelectronics Conference (INEC), 2010 3rd International , pp. 1042 -1043	inproceedings	DOI
Abstract: Rutile TiO2 nanorods were synthesized by surfactant assisted thermal hydrolysis of TiCl4 in an acidic solution. A uniform thin layer of carbon coating on the TiO2 nanorods was formed by in-situ reduction of carbon precursor molecules. The resulting TiO2@C nanorods were subjected to electrochemical measurements for testing their lithium electroactivity. The TiO2@C nanorods show a reversible capacity of #x223C;220 mA h g #x2212;1 at C/5 and #x223C;185 mA h g #x2212;1 at 1C, which are much better than those with bare TiO2 nanorods and commercial P25 nanoparticles measured under the same conditions. The significantly enhanced reversible capacity and rate capability evinces the dramatic increase of the average electron conductivity and structural stability of the anode composite material due to the thin carbon coating layer.
BibTeX: @inproceedings{2010_Qiu, author = {Yongcai Qiu and Wei Chen and Shihe Yang}, title = {Synthesis and high lithium electroactivity of rutile TiO2@C nanorods}, journal = {Nanoelectronics Conference (INEC), 2010 3rd International}, year = {2010}, pages = {1042 -1043}, doi = {http://dx.doi.org/10.1109/INEC.2010.5425048} }
Feinstein, D. & Thornton, M.	On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering [Abstract] [BibTeX]	2009	Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on , pp. 132 -138	inproceedings	DOI
Abstract: This paper proposes a framework that improves reversible logic synthesis by employing a dynamically determined variable order for quantum multiple-valued decision diagrams (QMDD). We demonstrate our approach through augmentation of the Miller-Maslov-Dueck (MMD) algorithm that processes the complete function specification in lexicographical order with our technique. We represent and minimize the complete specification with the QMDD and then synthesize the function specification based on the minimized variable order. The framework produces significantly smaller reversible circuits in many cases. Experimental results also show the effectiveness of using the QMDD size as a measure of the complexity of MVL and binary reversible circuits.
BibTeX: @inproceedings{2009_Feinstein, author = {Feinstein, D.Y. and Thornton, M.A.}, title = {On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering}, journal = {Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on}, year = {2009}, pages = {132 -138}, doi = {http://dx.doi.org/10.1109/ISMVL.2009.31} }
Grosse, D.; Wille, R.; Dueck, G. & Drechsler, R.	Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques [Abstract] [BibTeX]	2009	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 28 (5) , pp. 703 -715	article	DOI
Abstract: Synthesis of reversible logic has become a very important research area in recent years. Applications can be found in the domain of low-power design, optical computing, and quantum computing. In the past, several approaches have been introduced that synthesize reversible networks with respect to a given function. Most of these methods only approximate a minimal network representation. In this paper, exact algorithms for the synthesis of multiple-control Toffoli networks are presented, i.e., algorithms that guarantee to find a network with the minimal number of gates. Our iterative algorithms formulate the synthesis problem as a sequence of decision problems. The decision problems are encoded as Boolean satisfiability (SAT) or SAT modulo theory (SMT) instances, respectively. As soon as one of these instances becomes satisfiable, a Toffoli network representation for the given function has been found. We show that choosing the encoding for synthesis is crucial for the resulting runtimes. Furthermore, we discuss the principal limits of the SAT and SMT approaches. To overcome these limits, we propose a method using problem-specific knowledge during synthesis. In addition, better embeddings to make irreversible functions reversible are considered. For the resulting synthesis problems, an improvement is presented that reduces the overall runtime by automatically setting the constant inputs to their optimal values. Experimental results on a large set of benchmarks demonstrate the differences between three exact synthesis algorithms. In addition, a comparison with the best-known heuristic results is provided. In summary, the results show that, for some benchmarks, the heuristic approaches have already found the minimal network, while for other benchmarks, significantly smaller networks exist.
BibTeX: @article{2009_Grosse, author = {Grosse, D. and Wille, R. and Dueck, G.W. and Drechsler, R.}, title = {Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2009}, volume = {28}, number = {5}, pages = {703 -715}, doi = {http://dx.doi.org/10.1109/TCAD.2009.2017215} }
Hasan, M.; Islam, A. & Chowdhury, A.	Design and analysis of online testability of reversible sequential circuits [Abstract] [BibTeX]	2009	Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on , pp. 180 -185	inproceedings	DOI
Abstract: Reversible logic plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design and nanotechnology-based system. In this paper, we have proposed the online testability of reversible sequential circuits, which is first ever proposed in literature. On the way to propose the online testability of reversible sequential circuits, we have proposed an improved rail-check circuit that significantly improves the performance of the overall circuit in terms of gate cost and garbage cost parameters. We have also used our improved and efficient rail-check circuit to realize the testability of different benchmark circuits.
BibTeX: @inproceedings{2009_Hasan, author = {Hasan, M. and Islam, A.K.M.T. and Chowdhury, A.R.}, title = {Design and analysis of online testability of reversible sequential circuits}, journal = {Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on}, year = {2009}, pages = {180 -185}, doi = {http://dx.doi.org/10.1109/ICCIT.2009.5407143} }
Islam, S.; Rahman, M.; Begum, Z.; Hafiz, Z. & Al Mahmud, A.	Synthesis of Fault Tolerant Reversible Logic Circuits [Abstract] [BibTeX]	2009	Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on , pp. 1 -4	inproceedings	DOI
Abstract: Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 universal reversible logic gate, IG. It is a parity preserving reversible logic gate, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Finally, it is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
BibTeX: @inproceedings{2009_Islam, author = {Islam, S. and Rahman, M.M. and Begum, Z. and Hafiz, Z. and Al Mahmud, A.}, title = {Synthesis of Fault Tolerant Reversible Logic Circuits}, journal = {Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on}, year = {2009}, pages = {1 -4}, doi = {http://dx.doi.org/10.1109/CAS-ICTD.2009.4960883} }
Islam, M.; Rahman, M.; Begum, Z. & Hafiz, M.	Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders [Abstract] [BibTeX]	2009	Advances in Computational Tools for Engineering Applications, 2009. ACTEA '09. International Conference on , pp. 396 -401	inproceedings	DOI
Abstract: Irreversible logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed 16-bit high speed reversible adder will include IG gates for the realization of its basic building block. The IG gate is universal in the sense that it can be used to synthesize any arbitrary Boolean-functions. The IG gate is parity preserving, that is, the parity of the inputs matches the parity of the outputs. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Therefore, the proposed high speed adders will have the inherent opportunity of detecting errors in its output side. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
BibTeX: @inproceedings{2009_Islama, author = {Islam, M.S. and Rahman, M.M. and Begum, Z. and Hafiz, M.Z.}, title = {Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders}, journal = {Advances in Computational Tools for Engineering Applications, 2009. ACTEA '09. International Conference on}, year = {2009}, pages = {396 -401}, doi = {http://dx.doi.org/10.1109/ACTEA.2009.5227871} }
Khan, M. & Hasan, R.	Minimized reversible synthesis of non-reversible quinary logic function [Abstract] [BibTeX]	2009	Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on , pp. 186 -191	inproceedings	DOI
Abstract: Reversible multiple-valued logic circuit has several advantages over reversible binary logic circuit. In this paper, we propose a method of minimization of Galois field sum of products (GFSOP) expression for non-reversible quinary logic function. We also propose a method of reversible realization of quinary GFSOP expression as cascade of quinary reversible gates. Experimental results show that a significant minimization can be achieved using the proposed minimization method.
BibTeX: @inproceedings{2009_Khan, author = {Khan, M.H.A. and Hasan, R.}, title = {Minimized reversible synthesis of non-reversible quinary logic function}, journal = {Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on}, year = {2009}, pages = {186 -191}, doi = {http://dx.doi.org/10.1109/ICCIT.2009.5407142} }
Khan, M.; Biswas, A.; Chowdhury, S.; Hasan, M. & Khan, A.	Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output [Abstract] [BibTeX]	2009	Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on , pp. 98 -102	inproceedings	DOI
Abstract: We present a method of synthesizing ternary Galois field (GF(3)) based reversible/quantum logic circuits without any ancillary trits/qutrits and hence without any garbage outputs. We realize multi input ternary Toffoli gate and square functions of GF(3) variables using linear ion trap realizable Muthukrishnan-Stroud (M-S) gates and shift gates in the absence of ancillary qutrits. Then based on the Galois Field Sum of Products (GFSOP)expression of a multi-variable GF(3) function, we synthesize the corresponding circuit.
BibTeX: @inproceedings{2009_Khana, author = {Khan, M.M. and Biswas, A.K. and Chowdhury, S. and Hasan, M. and Khan, A.I.}, title = {Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output}, journal = {Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on}, year = {2009}, pages = {98 -102}, doi = {http://dx.doi.org/10.1109/ISMVL.2009.73} }
Lin, Q. & Nguyen, T.	Aptamer-based microfluidic biosensors [Abstract] [BibTeX]	2009	Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on , pp. 812 -814	inproceedings
Abstract: Micro- and nanofabrication has allowed the creation of ultra-sensitive, miniaturized, and inexpensive biosensors. These devices generally utilize chemical or biological receptors which recognize a particular compound of interest and transduce this recognition event into a measurable signal. Recent advances in RNA and DNA synthesis have enabled the use of aptamers, which are in-vitro generated oligonucleotides offering high affinity biomolecular recognition to a theoretically limitless variety of analytes. DNA and RNA aptamers have become increasingly popular in the biosensor community, to the extent that they have begun competing with more established affinity ligands including enzymes, lectins, and most immunoreceptors such as antibodies. We present an overview of our recent research effort in developing an aptamer-functionalized microfluidic platform that by design exploits the specificity and temperature-dependent reversibility of aptamers to enable enhanced biosensing. Using the specificity of aptamers, we demonstrate highly selective capture and enrichment of biomolecules. Employing thermally induced, reversible disruption of aptamer-target binding, we accomplish isocratic elution of the captured analytes and regeneration of the aptamer aptamer-functionalized surfaces, thereby eliminating the use of potentially harsh reagents. Using integrated microfluidic control, the eluted analytes are detected in a label-free fashion by mass spectrometric methods.
BibTeX: @inproceedings{2009_Lin, author = {Qiao Lin and Nguyen, T.}, title = {Aptamer-based microfluidic biosensors}, journal = {Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on}, year = {2009}, pages = {812 -814} }
Liu, G.; Pu, S.; Fan, C. & Liu, W.	Efficient Synthesis, Photochromism and Electrochemical Properties of a Novel 2,3-position Hybrid Diarylethene [Abstract] [BibTeX]	2009	Circuits, Communications and Systems, 2009. PACCS '09. Pacific-Asia Conference on , pp. 457 -460	inproceedings	DOI
Abstract: A novel 2,3-position hybrid diarylethene, 1-(2-methyl-5-phenyl -3-thienyl) -2-(3-methyl-5-phenyl-2-thienyl) perfluorocyclopentene (1 a), was synthesized, and its photochromic reactivity, fluorescent and electrochemical property were also investigated. The results showed that this compound exhibited reversible photochromism, changing from colorless to red after irradiation with UV light both in solution and in PMMA amorphous film. In hexane solution, the open-ring isomer of the diarylethene 1 exhibited relatively strong fluorescence at 440 nm when excited at 350 nm. The electrochemcial switching property can be potential use for electrochemistry data storage.
BibTeX: @inproceedings{2009_Liu, author = {Gang Liu and Shouzhi Pu and Congbin Fan and Weijun Liu}, title = {Efficient Synthesis, Photochromism and Electrochemical Properties of a Novel 2,3-position Hybrid Diarylethene}, journal = {Circuits, Communications and Systems, 2009. PACCS '09. Pacific-Asia Conference on}, year = {2009}, pages = {457 -460}, doi = {http://dx.doi.org/10.1109/PACCS.2009.78} }
Miller, D.; Wille, R. & Dueck, G.	Synthesizing Reversible Circuits for Irreversible Functions [Abstract] [BibTeX]	2009	Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on , pp. 749 -756	inproceedings	DOI
Abstract: Many reversible circuit synthesis procedures have been proposed. A common feature of most methods is that the initial specification must be a completely-specified reversible function. However, often the desired functionality is a, possibly incompletely-specified, irreversible function. In this paper, we consider how to fully automate the process of synthesizing a reversible function given an irreversible specification with particular emphasis on how to embed an irreversible function into a reversible specification. Systematic procedures are presented and results for benchmark problems show the methods produce very good results compared to earlier methods.
BibTeX: @inproceedings{2009_Miller, author = {Miller, D.M. and Wille, R. and Dueck, G.W.}, title = {Synthesizing Reversible Circuits for Irreversible Functions}, journal = {Digital System Design, Architectures, Methods and Tools, 2009. DSD '09. 12th Euromicro Conference on}, year = {2009}, pages = {749 -756}, doi = {http://dx.doi.org/10.1109/DSD.2009.186} }
Nower, N. & Chowdhury, A.	Realization of systolic array using ternary reversible gates [Abstract] [BibTeX]	2009	Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on , pp. 192 -196	inproceedings	DOI
Abstract: Multi valued logic synthesis is a very promising and affluent research area at present because of allowing designers to build much more efficient computers than the existing classical ones. Ternary logic synthesis research has got impetus in the recent years. Many existing literature are mainly perceptive to the realization of efficient ternary reversible processors. This research is based on the design of a reversible systolic array, which is one of the best examples of parallel processing, using micro level ternary Toffoli gate. General architecture of the ternary reversible systolic array multiplier is shown along with example. Lower bound for the garbage outputs produced in the proposed design and the quantum cost of the entire circuit is calculated here to prove the compactness of the design.
BibTeX: @inproceedings{2009_Nower, author = {Nower, N. and Chowdhury, A.R.}, title = {Realization of systolic array using ternary reversible gates}, journal = {Computers and Information Technology, 2009. ICCIT '09. 12th International Conference on}, year = {2009}, pages = {192 -196}, doi = {http://dx.doi.org/10.1109/ICCIT.2009.5407141} }
Sasanian, Z.; Saeedi, M.; Sedighi, M. & Zamani, M.	A cycle-based synthesis algorithm for reversible logic [Abstract] [BibTeX]	2009	Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific , pp. 745 -750	inproceedings	DOI
Abstract: Several algorithms have been proposed for the synthesis of reversible circuits. In this paper, a cycle-based synthesis algorithm for reversible logic, based on the NCT library, has been proposed. In other words, direct implementation of a single 3-cycle, a pair of 3-cycles and a pair of 2-cycles have been explored and used to propose an efficient Toffoli-based synthesis algorithm for reversible circuits. The synthesis algorithm decomposes a given large cycle into a set of single 3-cycles, pairs of 3-cycles and pair of 2-cycles and synthesizes the resulted cycles directly. Our experimental results show that the proposed synthesis algorithm can outperform the available 2-cycle-based approach about 34% on average. In addition, several discussions for the generalization of the proposed method to the 2m-cycles are given.
BibTeX: @inproceedings{2009_Sasanian, author = {Sasanian, Z. and Saeedi, M. and Sedighi, M. and Zamani, M.S.}, title = {A cycle-based synthesis algorithm for reversible logic}, journal = {Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific}, year = {2009}, pages = {745 -750}, doi = {http://dx.doi.org/10.1109/ASPDAC.2009.4796569} }
Takahashi, K. & Hirayama, T.	Reversible logic synthesis from positive Davio trees of logic functions [Abstract] [BibTeX]	2009	TENCON 2009 - 2009 IEEE Region 10 Conference , pp. 1 -4	inproceedings	DOI
Abstract: Considering the Landauer's principle, a reversible logic circuit is said to be energy conservation compared with conventional digital circuit. In this paper, we propose and implement a reversible logic synthesis algorithm utilizing the positive Davio trees of logic functions. We synthesize a reversible logic circuit by replacing the each node with reversible logic gates, and connecting them. Moreover, by sharing the nodes being able to share, we purpose the synthesis of circuits of the fewer gates, and the fewer garbage lines.
BibTeX: @inproceedings{2009_Takahashi, author = {Takahashi, K. and Hirayama, T.}, title = {Reversible logic synthesis from positive Davio trees of logic functions}, journal = {TENCON 2009 - 2009 IEEE Region 10 Conference}, year = {2009}, pages = {1 -4}, doi = {http://dx.doi.org/10.1109/TENCON.2009.5395805} }
Vasudevan, D.; Goudarzi, M.; Popovici, E. & Schellekens, M.	A Reversible MIPS multi-cycle control FSM design [Abstract] [BibTeX]	2009	Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on , pp. 336 -342	inproceedings	DOI
Abstract: Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced in this paper. Three FSMs namely original, reverse and reversible FSM of the MIPS control circuit is designed, synthesized and simulated. Synthesis and simulation results are provided for the three implementations. The overhead for designing the reversible FSM are log2(N)rceil conflict pins and one direction pin along with extra logic for inserting them.
BibTeX: @inproceedings{2009_Vasudevan, author = {Vasudevan, D. and Goudarzi, M. and Popovici, E. and Schellekens, M.}, title = {A Reversible MIPS multi-cycle control FSM design}, journal = {Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on}, year = {2009}, pages = {336 -342}, doi = {http://dx.doi.org/10.1109/ASQED.2009.5206242} }
Wille, R.; Grosse, D.; Dueck, G. & Drechsler, R.	Reversible Logic Synthesis with Output Permutation [Abstract] [BibTeX]	2009	VLSI Design, 2009 22nd International Conference on , pp. 189 -194	inproceedings	DOI
Abstract: Synthesis of reversible logic has become a very important research area. In recent years several algorithms--heuristic as well as exact ones--have been introduced in this area. Typically, they use the specification of a reversible function in terms of a truth table as input. Here, the position of the outputs are fixed. However, in general it is irrelevant, how the respective outputs are ordered. Thus, a synthesis methodology is proposed that determines for a given reversible function an equivalent circuit realization modulo output permutation. More precisely, the result of the synthesis process is a circuit realization whose output functions have been permuted in comparison to the original specification and the respective permutation vector. We show that this synthesis methodology may lead to significant smaller realizations. We apply Synthesis with Output Permutation (SWOP) to both, an exact and a heuristic synthesis algorithm. As our experiments show using the new synthesis paradigm leads to multiple control Toffoli networks that are smaller than the currently best known realizations.
BibTeX: @inproceedings{2009_Wille, author = {Wille, R. and Grosse, D. and Dueck, G.W. and Drechsler, R.}, title = {Reversible Logic Synthesis with Output Permutation}, journal = {VLSI Design, 2009 22nd International Conference on}, year = {2009}, pages = {189 -194}, doi = {http://dx.doi.org/10.1109/VLSI.Design.2009.40} }
Wille, R. & Drechsler, R.	BDD-based synthesis of reversible logic for large functions [Abstract] [BibTeX]	2009	Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE , pp. 270 -275	inproceedings
Abstract: Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a binary decision diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.
BibTeX: @inproceedings{2009_Willea, author = {Wille, R. and Drechsler, R.}, title = {BDD-based synthesis of reversible logic for large functions}, journal = {Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE}, year = {2009}, pages = {270 -275} }
Wille, R.; Grosse, D.; Frehse, S.; Dueck, G. & Drechsler, R.	Debugging of Toffoli networks [Abstract] [BibTeX]	2009	Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09. , pp. 1284 -1289	inproceedings
Abstract: Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible logic synthesis, testing, and verification have been investigated, debugging of reversible circuits has not yet been considered. The goal of debugging is to determine gates of an erroneous circuit that explain the observed incorrect behavior. In this paper we propose the first approach for automatic debugging of reversible Toffoli networks. Our method uses a formulation for the debugging problem based on Boolean satisfiability. We show the differences to classical (irreversible) debugging and present theoretical results. These are used to speed-up the debugging approach as well as to improve the resulting quality. Our method is able to find and to correct single errors automatically.
BibTeX: @inproceedings{2009_Willeb, author = {Wille, R. and Grosse, D. and Frehse, S. and Dueck, G.W. and Drechsler, R.}, title = {Debugging of Toffoli networks}, journal = {Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09.}, year = {2009}, pages = {1284 -1289} }
Xiao, X.Z.; Chen, L.X.; Fan, X.L.; Wang, X.H.; Chen, C.P.; Lei, Y.Q. & Wang, Q.D.	Direct synthesis of nanocrystalline NaAlH4 complex hydride for hydrogen storage [Abstract] [BibTeX]	2009	Applied Physics Letters Vol. 94 (4) , pp. 041907 -041907-3	article	DOI
Abstract: Nanocrystalline NaAlH4 was directly synthesized by ball milling NaH/Al with TiF3 catalyst under hydrogen pressure of 15 #x2013;25 bar within 50 h. It is found that the synthesized NaAlH4 exhibits a high reversible hydrogen capacity of 4.7 nbsp;wt #x2009;% with fast reaction kinetics. It can absorb about 3.5 nbsp;wt #x2009;% hydrogen even at ambient temperature. The Ti #x2013;Al #x2013;H active species formed during reactive ball milling may act as catalyzing agent for hydrogen dissociation/recombination during in situ hydrogenation process and subsequent hydriding/dehydriding cycle.
BibTeX: @article{2009_Xiao, author = {Xiao, X. Z. and Chen, L. X. and Fan, X. L. and Wang, X. H. and Chen, C. P. and Lei, Y. Q. and Wang, Q. D.}, title = {Direct synthesis of nanocrystalline NaAlH4 complex hydride for hydrogen storage}, journal = {Applied Physics Letters}, year = {2009}, volume = {94}, number = {4}, pages = {041907 -041907-3}, doi = {http://dx.doi.org/10.1063/1.3076104} }
Yan, P.; Pu, S.; Liu, G. & Liu, W.	Synthesis, Optoelectronic Property and Application for Optical Recording of a New Diarylethene [Abstract] [BibTeX]	2009	Circuits, Communications and Systems, 2009. PACCS '09. Pacific-Asia Conference on , pp. 481 -484	inproceedings	DOI
Abstract: A novel photochromic diarylethene, 1-[2-methyl-5-(4-trifluoromethylphenyl)-3-thienyl]-2-[2-methyl-5-(4-chlorophenyl)-3-thienyl] perfluorocyclopentene(1a), was synthesized, and its photochromic and fluorescent properties were investigated in detail. This compound exhibited reversible photochromism, changing from colorless to blue after irradiation with UV light both in solution and in poly-methyl methacrylate (PMMA) amorphous film. Also, it showed strong fluorescence and gave a bathochromic shift upon increasing concentration in hexane. At last, using diarylethene 1b/PMMA film as recording medium, polarization holographic optical recording was performed perfectly by a He-Ne laser with 633 nm wavelength. The results demonstrated that it can be potentially used as polarization holographic optical recording medium.
BibTeX: @inproceedings{2009_Yan, author = {Peijian Yan and Shouzhi Pu and Gang Liu and Weijun Liu}, title = {Synthesis, Optoelectronic Property and Application for Optical Recording of a New Diarylethene}, journal = {Circuits, Communications and Systems, 2009. PACCS '09. Pacific-Asia Conference on}, year = {2009}, pages = {481 -484}, doi = {http://dx.doi.org/10.1109/PACCS.2009.84} }
Zhang, M.; Zhao, S. & Wang, X.	Automatic synthesis of reversible logic circuit based on genetic algorithm [Abstract] [BibTeX]	2009	Intelligent Computing and Intelligent Systems, 2009. ICIS 2009. IEEE International Conference on Vol. 3 , pp. 542 -546	inproceedings	DOI
Abstract: The reversible logic circuits (RLC) are a sort of novel circuits which can avoid the information loss and energy dissipation by implementing the reversible logic operations. RLC prohibit the feedback and don't have the fan-out, so the synthesis methods of RLC are very different from the existing irreversible logic circuits. In this paper, evolutionary design techniques are applied to the synthesis of RLC, and then an automatic synthesis approach of RLC based on genetic algorithm is proposed. Firstly, some appropriate reversible logic gates are chosen as the building-blocks, and a computational array model is built for the synthesis of RLC. According to the array model, the synthesis problems are modeled as the constrained multi-objective optimization problems which are converted into their single-objective equivalents by the weighted sum of objective functions. Then, the single-objective equivalents are solved by a specialized genetic algorithm. The experimental results verify the capability of automatic synthesis of the proposed approach, and show that the proposed approach is feasible and effective.
BibTeX: @inproceedings{2009_Zhang, author = {Mingming Zhang and Shuguang Zhao and Xu Wang}, title = {Automatic synthesis of reversible logic circuit based on genetic algorithm}, journal = {Intelligent Computing and Intelligent Systems, 2009. ICIS 2009. IEEE International Conference on}, year = {2009}, volume = {3}, pages = {542 -546}, doi = {http://dx.doi.org/10.1109/ICICISYS.2009.5358132} }
Zhang, M.; Zhao, S. & Wang, X.	Multi-objective Reversible Logic Gate-level Evolutionary Synthesis Using Multi-objective Adaptive Discrete Differential Evolution [Abstract] [BibTeX]	2009	Intelligent Information Technology Application, 2009. IITA 2009. Third International Symposium on Vol. 2 , pp. 533 -536	inproceedings	DOI
Abstract: The reversible logic synthesis is a multi-objective optimization problem with rigorous constraints such as prohibiting the feedback and fan-out, and the same number of inputs and outputs, so it is difficult to be solved by general synthesis methods. Moreover, the synthesis methods of reversible logic circuits are very different from that of existing irreversible logic circuits. To make improvements in the capability and effectiveness of reversible logic synthesis, this paper proposes an algorithm of reversible logic gate-level evolutionary synthesis using multi-objective adaptive discrete differential evolution based on Pareto optimal. The synthesis experiments are conducted for a set of benchmark reversible logic circuits which are widely used in the reversible logic synthesis tests. The experiment results show that the proposed synthesis algorithm can give attention to multiple synthesis objectives at the same time, and has the capability to automatically synthesize the better reversible logic circuits, which verifies the feasibility and effectiveness of the proposed synthesis algorithm.
BibTeX: @inproceedings{2009_Zhanga, author = {Mingming Zhang and Shuguang Zhao and Xu Wang}, title = {Multi-objective Reversible Logic Gate-level Evolutionary Synthesis Using Multi-objective Adaptive Discrete Differential Evolution}, journal = {Intelligent Information Technology Application, 2009. IITA 2009. Third International Symposium on}, year = {2009}, volume = {2}, pages = {533 -536}, doi = {http://dx.doi.org/10.1109/IITA.2009.249} }
Zheng, Y. & Huang, C.	A novel Toffoli network synthesis algorithm for reversible logic [Abstract] [BibTeX]	2009	Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific , pp. 739 -744	inproceedings	DOI
Abstract: Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input output correspondence which makes the logic synthesis for reversible functions differs greatly from traditional Boolean functions. Exact synthesis methods can provide optimal solutions in terms of the total number of reversible gates in the synthesis results. Unfortunately, they may suffer from long computation time, due to the fact that the search space is likely to grow exponentially as the circuit size increases. Therefore, in this paper, we propose an efficient synthesis heuristic which provides high quality synthesis results of Toffoli network in more reasonable computation time. We use a weighted, directed graph for reversible function representation and complexity measurement. The proposed algorithm maximally decreases function complexity during synthesis steps. It has the ability to climb out of local minimums and guarantees algorithm convergence. The experimental results show that our algorithm can achieve optimal or very close to optimal solutions with computation time several orders of magnitude less than the exact methods. Compared with other heuristics, our method demonstrates superior performance in terms of reversible gate count as well as computation time.
BibTeX: @inproceedings{2009_Zheng, author = {Yexin Zheng and Chao Huang}, title = {A novel Toffoli network synthesis algorithm for reversible logic}, journal = {Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific}, year = {2009}, pages = {739 -744}, doi = {http://dx.doi.org/10.1109/ASPDAC.2009.4796568} }
Ardestani, E.; Zamani, M. & Sedighi, M.	A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits [Abstract] [BibTeX]	2008	Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on , pp. 803 -806	inproceedings	DOI
Abstract: In this paper, a simple and fast algorithm for the synthesis of reversible circuits is presented. This algorithm considers the synthesis process as a kind of sorting problem, generating a reversible circuit composed of CNOT-based gates. We prove that the proposed algorithm converges for any given specification. The empirical results of realizing examples discussed in the literature are reported. The results show that the algorithm leads to a near optimum solution for all 3*3 specifications and very good results for other larger specifications in much fewer steps compared to the search based and other previous algorithms.
BibTeX: @inproceedings{2008_Ardestani, author = {Ardestani, E.K. and Zamani, M.S. and Sedighi, M.}, title = {A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits}, journal = {Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on}, year = {2008}, pages = {803 -806}, doi = {http://dx.doi.org/10.1109/DSD.2008.95} }
Changjun, H.; Jiale, D.; Danqun, H.; Guixiang, R.; Wei, L. & Yujuan, D.	Porphyrin-functionalized single-walled nanotubes solution for DMMP detection [Abstract] [BibTeX]	2008	Nanoelectronics Conference, 2008. INEC 2008. 2nd IEEE International , pp. 266 -270	inproceedings	DOI
Abstract: A novel material of porphyrin functionalized Single-walled Nanotubes was employed on optical property research, aimed to DMMP detection, a simulant to Sarin. The composites were synthesis by condensation Zn-Tetraphenylporphyrin and bonding on SWNTs with non-covalent methods. The results were well characterized with TEM, AFM, as well as UV-visible measurements, demonstrated the diameter of nanotubes we used was estimated to range ~0.9-1.5nm, and the existence of nano-composites. It proved that with using porphyrin-functionalized single-walled carbon nanotubes in DMF solution, the materials were reversible and capable of detecting DMMP (Sigma, 97%) at 9 ppb levels by UV-visible measurements.
BibTeX: @inproceedings{2008_Changjun, author = {Hou Changjun and Dong Jiale and Huo Danqun and Ren Guixiang and Luo Wei and Duan Yujuan}, title = {Porphyrin-functionalized single-walled nanotubes solution for DMMP detection}, journal = {Nanoelectronics Conference, 2008. INEC 2008. 2nd IEEE International}, year = {2008}, pages = {266 -270}, doi = {http://dx.doi.org/10.1109/INEC.2008.4585483} }
Grosse, D.; Wille, R.; Dueck, G. & Drechsler, R.	Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares [Abstract] [BibTeX]	2008	Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on , pp. 214 -219	inproceedings	DOI
Abstract: Compact realizations of reversible logic functions are of interest in the design of quantum computers. In this paper we present an exact synthesis algorithm, based on Boolean satisfiability (SAT), that finds the minimal elementary quantum gate realization for a given reversible function. Since these gates work in terms of qubits, a multi-valued encoding is proposed. Don't care conditions appear naturally in many reversible functions. Constant inputs are often required when a function is embedded into a reversible one. The proposed algorithm takes full advantage of don't care conditions and automatically sets the constant inputs to their optimal values. The effectiveness of the algorithm is shown on a set of benchmark functions.
BibTeX: @inproceedings{2008_Grosse, author = {Grosse, D. and Wille, R. and Dueck, G.W. and Drechsler, R.}, title = {Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares}, journal = {Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on}, year = {2008}, pages = {214 -219}, doi = {http://dx.doi.org/10.1109/ISMVL.2008.42} }
Hasan, M.	Low-cost realization of toffoli gate for the low-cost synthesis of quantum ternary logic functions [Abstract] [BibTeX]	2008	Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on , pp. 259 -263	inproceedings	DOI
Abstract: Reversible quantum computer system is one of the best choices for future computer systems. Multiple-valued logic especially ternary logic is a good candidate for the realization of reversible quantum computer. An efficient logic synthesis mechanism is essential for the low-cost realization. Toffoli gate is an important gate for quantum logic synthesis. It is the basic element for the Galois Field Sum of Product (GFSOP) expression based logic synthesis mechanism. So, for low-cost realization of any ternary logic function, a low-cost implementation of Toffoli gate is very necessary. This paper shows a low-cost, practically realizable, and efficient realization of 3-qutrit ternary Toffoli gate by using ion-trap realizable Muthukrishnan-Stroud gate. This realization is more efficient and less costly than other realizations.
BibTeX: @inproceedings{2008_Hasan, author = {Hasan, M.M.}, title = {Low-cost realization of toffoli gate for the low-cost synthesis of quantum ternary logic functions}, journal = {Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on}, year = {2008}, pages = {259 -263}, doi = {http://dx.doi.org/10.1109/ICCITECHN.2008.4803024} }
Khanoma, R.; Kamalb, T. & Khana, M.	Genetic Algorithm based synthesis of ternary Reversible/Quantum circuit [Abstract] [BibTeX]	2008	Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on , pp. 270 -275	inproceedings	DOI
Abstract: Reversible/quantum circuits are believed to be one of the future computer technologies. In this paper, a genetic algorithm (GA) based synthesis of ternary reversible/quantum circuits using Muthukrishnan-Stroud gates is presented. The circuit generated by GA may contain redundant gates. We have used post GA reduction to eliminate these redundant gates. We have experimented with ternary half-adder circuit. The proposed GA converges for many combinations of crossover and mutation.
BibTeX: @inproceedings{2008_Khanoma, author = {Khanoma, R. and Kamalb, T. and Khana, M.}, title = {Genetic Algorithm based synthesis of ternary Reversible/Quantum circuit}, journal = {Computer and Information Technology, 2008. ICCIT 2008. 11th International Conference on}, year = {2008}, pages = {270 -275}, doi = {http://dx.doi.org/10.1109/ICCITECHN.2008.4803043} }
Li, Z.; Chen, H.; Xu, B.; Liu, W.; Song, X. & Xue, X.	Fast algorithm for 4-qubit reversible logic circuits synthesis [Abstract] [BibTeX]	2008	Evolutionary Computation, 2008. CEC 2008. (IEEE World Congress on Computational Intelligence). IEEE Congress on , pp. 2202 -2207	inproceedings	DOI
Abstract: Owing to the exponential nature of the memory or run-tune complexity, many existing methods can only synthesize 3-qubit circuits, however, (G.W. Yang et al., 2005) can achieve 12 steps for the CNP (controlled-Not gate, NOT gate and Peres gate) library in 4-qubit circuit synthesis with mini-length by using an enhanced bi-directional synthesis approach. We mainly absorb the ideas of our 3-qubit synthesis algorithms based on hash table and present a novel and efficient algorithm which can construct almost all optimal 4-qubit reversible logic circuits with various types of gates and mini-length cost based on constructing the shortest coding and the specific topological compression, whose lossless compression ratios of the space of n-qubit circuits is near 2timesn!. Our algorithm has created all 3120218828 optimal 4-qubit circuits whose length is less than 9 for the CNT (Toffoli gate) library, and it can quickly achieve 16 steps through cascading created circuits. To the best of our knowledge, there are no other algorithms to achieve the contribution.
BibTeX: @inproceedings{2008_Li, author = {Zhiqiang Li and Hanwu Chen and Baowen Xu and Wenjie Liu and Xiaoyu Song and Xilin Xue}, title = {Fast algorithm for 4-qubit reversible logic circuits synthesis}, journal = {Evolutionary Computation, 2008. CEC 2008. (IEEE World Congress on Computational Intelligence). IEEE Congress on}, year = {2008}, pages = {2202 -2207}, doi = {http://dx.doi.org/10.1109/CEC.2008.4631091} }
Li, Z.; Chen, H.; Xu, B.; Song, X. & Xue, X.	Effective Hash-Based Algorithm for Reversible Logic Circuits Synthesis with Minimum Cost [Abstract] [BibTeX]	2008	Natural Computation, 2008. ICNC '08. Fourth International Conference on Vol. 3 , pp. 623 -627	inproceedings	DOI
Abstract: We present an effective algorithm which can construct optimal 3-qubit reversible logic circuits for any given reversible logic gates and costs by constructing a minimal perfect hash function. We also present an algorithm which can automatically construct quantum gate library. In the experiments on 3-qubit synthesis, our algorithm synthesizes all optimal reversible circuits with extremely fast speed--the average speed which synthesizes circuits with minimum cost is 365 times faster than that of best result.
BibTeX: @inproceedings{2008_Lia, author = {Zhiqiang Li and Hanwu Chen and Baowen Xu and Xiaoyu Song and Xiling Xue}, title = {Effective Hash-Based Algorithm for Reversible Logic Circuits Synthesis with Minimum Cost}, journal = {Natural Computation, 2008. ICNC '08. Fourth International Conference on}, year = {2008}, volume = {3}, pages = {623 -627}, doi = {http://dx.doi.org/10.1109/ICNC.2008.191} }
Li, Z.; Chen, H.; Xu, B.; Song, X. & Xue, X.	An Algorithm for Synthesis of Optimal 3-qubit Reversible Circuits Based on Bit Operation [Abstract] [BibTeX]	2008	Genetic and Evolutionary Computing, 2008. WGEC '08. Second International Conference on , pp. 455 -458	inproceedings	DOI
Abstract: We use bit operation to construct the novel and perfect Hash function and present an efficient algorithm which can construct optimal quantum reversible logic circuits with various types of gates by using the Hash table and produce quantum circuits with minimal cost in theory. Judging by the internationally recognized reversible functions of three variables, the algorithm not only synthesizes all optimal reversible logic circuits, but also runs extremely faster than other ones. The experimental results show that the average speed of the algorithm which synthesizes circuit with minimum length is 69.8 times that of currently best result [9].
BibTeX: @inproceedings{2008_Lib, author = {Zhiqiang Li and Hanwu Chen and Baowen Xu and Xiaoyu Song and Xiling Xue}, title = {An Algorithm for Synthesis of Optimal 3-qubit Reversible Circuits Based on Bit Operation}, journal = {Genetic and Evolutionary Computing, 2008. WGEC '08. Second International Conference on}, year = {2008}, pages = {455 -458}, doi = {http://dx.doi.org/10.1109/WGEC.2008.37} }
Mohammadi, M.; Eshghi, M. & Haghparast, M.	On design of multiple-valued sequential reversible circuits for nanotechnology based systems [Abstract] [BibTeX]	2008	TENCON 2008 - 2008 IEEE Region 10 Conference , pp. 1 -6	inproceedings	DOI
Abstract: Multiple-valued reversible logic is an emerging area in reversible and quantum logic circuit synthesis. Multiple-valued reversible logic circuits can potentially reduce the width of the reversible or quantum circuit which is a limitation in current quantum technology. In this paper we propose a method to synthesize the multiple-valued reversible sequential circuits. Implementations for ternary D and T flip flops and edge triggered D flip flop are proposed. Synthesis of generalized fanout circuit and generalized r-valued T flip flop are also presented.
BibTeX: @inproceedings{2008_Mohammadi, author = {Mohammadi, M. and Eshghi, M. and Haghparast, M.}, title = {On design of multiple-valued sequential reversible circuits for nanotechnology based systems}, journal = {TENCON 2008 - 2008 IEEE Region 10 Conference}, year = {2008}, pages = {1 -6}, doi = {http://dx.doi.org/10.1109/TENCON.2008.4766407} }
Mohammadi, M. & Eshghi, M.	Behavioral description of quantum V and V+ gates to design quantum logic circuits [Abstract] [BibTeX]	2008	Systems, Signals and Devices, 2008. IEEE SSD 2008. 5th International Multi-Conference on , pp. 1 -5	inproceedings	DOI
Abstract: Quantum gates which are represented by unitary matrices have potentials to implement reversible logic circuits. V and V+ gates are two well known quantum gates which are used to synthesize the reversible logic circuits. In this paper we have used behavioral description of these gates, instead of unitary matrix description, to synthesize reversible logic circuits. By this method, V and V+ gates are shown in the truth table form. Results show that bigger circuits with more number of gates can be synthesized using proposed method. Some benchmarks of reversible logic circuits are also optimized and compared to other works.
BibTeX: @inproceedings{2008_Mohammadia, author = {Mohammadi, M. and Eshghi, M.}, title = {Behavioral description of quantum V and V+ gates to design quantum logic circuits}, journal = {Systems, Signals and Devices, 2008. IEEE SSD 2008. 5th International Multi-Conference on}, year = {2008}, pages = {1 -5}, doi = {http://dx.doi.org/10.1109/SSD.2008.4632850} }
Mohammadi, M.; Eshghi, M. & Bahrololoom, A.	Behavioral model of V and V+ gates to implement the reversible circuits using quantum gates [Abstract] [BibTeX]	2008	TENCON 2008 - 2008 IEEE Region 10 Conference , pp. 1 -6	inproceedings	DOI
Abstract: This paper addresses using quantum gates to implement binary reversible logic circuits. We propose behavioral models for well known V and V+ quantum gates. Our proposed representation is used to synthesize reversible logic circuits instead of using the known unitary matrix form of quantum gates. This technique allows V and V+ gates to be represented in truth table forms. Results show that our technique can be used to synthesize circuits with bigger sizes and gate counts in compare with unitary matrix form of these gates. Several reversible circuit benchmarks are optimized and compared to related works.
BibTeX: @inproceedings{2008_Mohammadib, author = {Mohammadi, M. and Eshghi, M. and Bahrololoom, A.}, title = {Behavioral model of V and V+ gates to implement the reversible circuits using quantum gates}, journal = {TENCON 2008 - 2008 IEEE Region 10 Conference}, year = {2008}, pages = {1 -6}, doi = {http://dx.doi.org/10.1109/TENCON.2008.4766409} }
Naderpour, F. & Vafaei, A.	Reversible multipliers: Decreasing the depth of the circuit [Abstract] [BibTeX]	2008	Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on , pp. 306 -310	inproceedings	DOI
Abstract: There are many arithmetic operations which are performed, on a computer arithmetic unit, through the use of multipliers (e.g., exponential and trigonometric functions). Consequently, optimized multipliers are on demand while designing an arithmetic unit. On the other hand, given the advent of quantum computer and reversible logic, design and implementation of digital circuits in this logic has gained popularity. In reversible circuit design, decreasing three parameters is of interest: quantum cost, depth of the circuit and the number of garbage outputs. In this paper, we propose a novel reversible multiplier with the aim of decreasing the depth of the circuit while neither scarifying any extra quantum cost nor garbage outputs. The partial products, as is the case for prior works, are generated in parallel using Peres gates and thereafter a reversible multi-operand adder consisting of reversible full-adders and half-adders produces the final product.
BibTeX: @inproceedings{2008_Naderpour, author = {Naderpour, F. and Vafaei, A.}, title = {Reversible multipliers: Decreasing the depth of the circuit}, journal = {Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on}, year = {2008}, pages = {306 -310}, doi = {http://dx.doi.org/10.1109/ICECE.2008.4769222} }
Rahaman, H.; Kole, D.; Das, D. & Bhattacharya, B.	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set [Abstract] [BibTeX]	2008	VLSI Design, 2008. VLSID 2008. 21st International Conference on , pp. 163 -168	inproceedings	DOI
Abstract: Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Newer technologies like ion trapping or nuclear magnetic resonance are required to emulate quantum gates. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely, single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. In this paper, it is shown that in an (n times n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate yields an easily testable design, which admits a universal test set of size (n +1) that detects all SMGFs, RGFs, and PMGFs in the circuit.
BibTeX: @inproceedings{2008_Rahaman, author = {Rahaman, H. and Kole, D.K. and Das, D.K. and Bhattacharya, B.B.}, title = {On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set}, journal = {VLSI Design, 2008. VLSID 2008. 21st International Conference on}, year = {2008}, pages = {163 -168}, doi = {http://dx.doi.org/10.1109/VLSI.2008.106} }
Song, T.; Wang, S. & Wang, X.	The design of reversible gate and reversible sequential circuit based on DNA computing [Abstract] [BibTeX]	2008	Intelligent System and Knowledge Engineering, 2008. ISKE 2008. 3rd International Conference on Vol. 1 , pp. 114 -118	inproceedings	DOI
Abstract: Recently, the parallel computing power and ability of storing the information in nano scale have made the use of DNA molecules in a perfect computing paradigm. And the reversible logic has been taken as a significant paradigm in low power computing and it plays an important role in the synthesis of circuits for quantum computing. In this article, the reversible logic is proposed to be simulated by using DNA molecules and bio-chemistry operations: the input and the output of a reversible gate or a reversible sequential circuit are both DNA sequences, and the computing progresses correspond to the bio-chemistry operations. By sticking system and enzyme system, two kinds of DNA reversible gate are simulated, which are both called as the DNA Fredkin gate. Then the reversible sequential circuit can be simulated easily by using DNA Fredkin gates. And the DNA Fredkin gate can also be used for designing the optimal reversible sequential circuits. That must be a new computing model in both DNA computing and quantum computing.
BibTeX: @inproceedings{2008_Song, author = {Tao Song and Shudong Wang and Xun Wang}, title = {The design of reversible gate and reversible sequential circuit based on DNA computing}, journal = {Intelligent System and Knowledge Engineering, 2008. ISKE 2008. 3rd International Conference on}, year = {2008}, volume = {1}, pages = {114 -118}, doi = {http://dx.doi.org/10.1109/ISKE.2008.4730909} }
Wille, R.; Grosse, D.; Teuber, L.; Dueck, G. & Drechsler, R.	RevLib: An Online Resource for Reversible Functions and Reversible Circuits [Abstract] [BibTeX]	2008	Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on , pp. 220 -225	inproceedings	DOI
Abstract: Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, results are often documented only in terms of gate counts or quantum costs, rather than presenting the specific circuit. In this paper RevLib (www.revlib.org) is introduced, an online resource for reversible functions and reversible circuits. RevLib provides a large database of functions with respective circuit realizations. RevLib is designed to ease the evaluation of new methods and facilitate the comparison of results. In addition, tools are introduced to support researchers in evaluating their algorithms and documenting their results.
BibTeX: @inproceedings{2008_Wille, author = {Wille, R. and Grosse, D. and Teuber, L. and Dueck, G.W. and Drechsler, R.}, title = {RevLib: An Online Resource for Reversible Functions and Reversible Circuits}, journal = {Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on}, year = {2008}, pages = {220 -225}, doi = {http://dx.doi.org/10.1109/ISMVL.2008.43} }
Wille, R.; Grosse, D.; Soeken, M. & Drechsler, R.	Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability [Abstract] [BibTeX]	2008	Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual , pp. 411 -416	inproceedings	DOI
Abstract: Optimization problems can be solved using Boolean satisfiability by mapping them to a sequence of decision problems. Therefore, in the last years several encodings have been developed. Independently, also new solvers have been introduced lifting Boolean satisfiability to higher levels of abstraction, e.g. SAT modulo theories (SMT) solvers and word level solvers. Both support bit-vector logic and thus allow more compact encodings of the problems. In this paper we investigate the efficiency of these new solver paradigms applied to optimization problems. We show for two case studies - graph coloring and exact synthesis of reversible logic - that the resulting problem instances can be reduced with respect to the size. In addition for the synthesis problem significant run-time improvements can be achieved.
BibTeX: @inproceedings{2008_Willea, author = {Wille, R. and Grosse, D. and Soeken, M. and Drechsler, R.}, title = {Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability}, journal = {Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual}, year = {2008}, pages = {411 -416}, doi = {http://dx.doi.org/10.1109/ISVLSI.2008.82} }
Wille, R.; Le, H.; Dueck, G. & Grosse, D.	Quantified Synthesis of Reversible Logic [Abstract] [BibTeX]	2008	Design, Automation and Test in Europe, 2008. DATE '08 , pp. 1015 -1020	inproceedings	DOI
Abstract: In the last years synthesis of reversible logic functions has emerged as an important research area. Other fields such as low-power design, optical computing and quantum computing benefit directly from achieved improvements. Recently, several approaches for exact synthesis of Toffoli networks have been proposed. They all use Boolean satisfiability to solve the underlying synthesis problem. In this paper a new exact synthesis approach based on Quantified Boolean Formula (QBF) satisfiability - a generalization of Boolean satisfiability - is presented. Besides the application of QBF solvers, we propose Binary Decision Diagrams to solve the quantified problem formulation. This allows to easily support different gate libraries during synthesis. In addition, all minimal networks are found in a single step and the best one with respect to quantum costs can be chosen. Experimental results confirm that the new technique is faster than the best previously known approach and leads to cheaper realizations in terms of quantum costs.
BibTeX: @inproceedings{2008_Willeb, author = {Wille, R. and Le, H.M. and Dueck, G.W. and Grosse, D.}, title = {Quantified Synthesis of Reversible Logic}, journal = {Design, Automation and Test in Europe, 2008. DATE '08}, year = {2008}, pages = {1015 -1020}, doi = {http://dx.doi.org/10.1109/DATE.2008.4484814} }
ying Zhang, X.; li Wang, L. & gong Zhou, X.	Efficient RM conversion algorithm for large multiple output functions [Abstract] [BibTeX]	2008	Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on , pp. 2300 -2303	inproceedings	DOI
Abstract: RM (Reed-Muller) expansions have shown advantages compared with the traditional SOP (Sum-of-Products) forms in the areas of arithmetic logic, reversible logic synthesis and Boolean quantum circuit design. A new algorithm is presented for the conversion between SOP and RM forms of multiple output functions. This procedure is based on the cube set expressions and therefore independent on number of input variables. A verification method is also proposed to make sure the algorithm is correct. The experimental results show that the conversion algorithm is effective in terms of time for very large Boolean functions up to 199 inputs and 67 outputs.
BibTeX: @inproceedings{2008_Zhang, author = {Xiao-ying Zhang and Ling-li Wang and Xue-gong Zhou}, title = {Efficient RM conversion algorithm for large multiple output functions}, journal = {Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on}, year = {2008}, pages = {2300 -2303}, doi = {http://dx.doi.org/10.1109/ICSICT.2008.4735030} }
Chuang, M.-L. & Wang, C.-Y.	Synthesis of Reversible Sequential Elements [Abstract] [BibTeX]	2007	Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific , pp. 420 -425	inproceedings	DOI
Abstract: To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as D latch, JK latch, and T latch. Based on these reversible latches, we also construct the designs of the corresponding flip-flops. Comparing with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs is considerably reduced.
BibTeX: @inproceedings{2007_Chuang, author = {Min-Lun Chuang and Chun-Yao Wang}, title = {Synthesis of Reversible Sequential Elements}, journal = {Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific}, year = {2007}, pages = {420 -425}, doi = {http://dx.doi.org/10.1109/ASPDAC.2007.358022} }
Das, T.; Mukherjee, R.; Nudehi, S. & Chatterjee, A.	Design of Switching Laws for Shared-Sensing and Control by Reversible Transducers [Abstract] [BibTeX]	2007	American Control Conference, 2007. ACC '07 , pp. 1395 -1400	inproceedings	DOI
Abstract: In this paper we propose the concept of shared-sensing for reversible transducers. In shared- sensing, the transducers switch between sensing and actuation modes, which is different from self-sensing where sensing and actuation are performed simultaneously. Both shared-sensing and self-sensing offer to reduce the number of transducers and provide collocation. However, our initial investigations indicate that shared-sensing has many advantages as compared to self-sensing. In this paper we develop observer based control design for systems with shared-sensing transducers. Through simulations and experimental results we demonstrate the simplicity and effectiveness with which shared-sensing and control can be implemented.
BibTeX: @inproceedings{2007_Das, author = {Das, T. and Mukherjee, R. and Nudehi, S. and Chatterjee, A.}, title = {Design of Switching Laws for Shared-Sensing and Control by Reversible Transducers}, journal = {American Control Conference, 2007. ACC '07}, year = {2007}, pages = {1395 -1400}, doi = {http://dx.doi.org/10.1109/ACC.2007.4282552} }
Feinstein, D.; Thornton, M. & Nair, V.	Prefix Parallel Adder Virtual Implementation in Reversible Logic [Abstract] [BibTeX]	2007	Region 5 Technical Conference, 2007 IEEE , pp. 74 -80	inproceedings	DOI
Abstract: This paper demonstrates a simplified approach for reversible logic synthesis based on direct translation of the circuit VHDL description into virtual Fredkin gates. We investigate the size and speed of such a reversible logic implementation of the Brent-Kung Parallel Prefix Adder (PPA) in comparison to a standard logic implementation. Using the Altera Corporation's Quartic II synthesis and simulation tool, we show that our virtual reversible logic implementation follows the O(log2n) delay and O(n) cost of the standard logic implementation.
BibTeX: @inproceedings{2007_Feinstein, author = {Feinstein, D.Y. and Thornton, M.A. and Nair, V.S.S.}, title = {Prefix Parallel Adder Virtual Implementation in Reversible Logic}, journal = {Region 5 Technical Conference, 2007 IEEE}, year = {2007}, pages = {74 -80}, doi = {http://dx.doi.org/10.1109/TPSD.2007.4380355} }
Maslov, D. & Miller, D.	Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits [Abstract] [BibTeX]	2007	Computers Digital Techniques, IET Vol. 1 (2) , pp. 98 -104	article	DOI
Abstract: A breadth-first search method for determining optimal three-qubit circuits composed of quantum NOT, CNOT, controlled-V and controlled-V + (NCV) gates is introduced. Results are presented for simple gate count and for technology-motivated cost metrics. The optimal NCV circuits are also compared with NCV circuits derived from optimal NOT, CNOT and Toffoli (NCT) gate circuits. This work provides basic results and motivation for continued study of the direct synthesis of NCV circuits, and establishes relations between function realizations in different circuit cost metrics
BibTeX: @article{2007_Maslov, author = {Maslov, D. and Miller, D.M.}, title = {Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits}, journal = {Computers Digital Techniques, IET}, year = {2007}, volume = {1}, number = {2}, pages = {98 -104}, doi = {http://dx.doi.org/10.1049/iet-cdt:20060070} }
Qian, H. & Luo, J.	Vanadia-based equilibrium-thickness amorphous films on anatase (101) surfaces [Abstract] [BibTeX]	2007	Applied Physics Letters Vol. 91 (6) , pp. 061909 -061909-3	article	DOI
Abstract: Nanometer-thick, surficial amorphous films are found to form in a model #x201c;monolayer #x201d; catalyst system: vanadia on TiO2 anatase (101) surfaces. These films exhibit a self-selecting or #x201c;equilibrium #x201d; thickness; once a thermodynamic equilibrium is reached, the film thickness, which corresponds to the Gibbsian surface excess of vanadia adsorbates, is independent of synthesis methods, the fraction of secondary vanadia phase, and the heat treatment history. These (multilayer) adsorbate films are largely amorphous (quasiliquid) at subeutectic temperatures, where analogies to premelting and prewetting phenomena are made. Reversible film thickness versus temperature (with a hysteresis loop) is observed and explained from a force-balance model.
BibTeX: @article{2007_Qian, author = {Qian, Haijun and Luo, Jian}, title = {Vanadia-based equilibrium-thickness amorphous films on anatase (101) surfaces}, journal = {Applied Physics Letters}, year = {2007}, volume = {91}, number = {6}, pages = {061909 -061909-3}, doi = {http://dx.doi.org/10.1063/1.2768315} }
Saeedi, M.; Zamani, M. & Sedighi, M.	On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement [Abstract] [BibTeX]	2007	VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on , pp. 428 -436	inproceedings	DOI
Abstract: In this paper, the behavior of substitution-based reversible circuit synthesis methods is studied. We analyze one of the most recent search-based synthesis algorithms to improve its quality by adding some new non-trivial substitutions. Furthermore, it is shown that the order of factor substitution affects the depth of search tree significantly. In addition, we consider the number of terms in positive polarity Reed-Muller (PPRM) expansions during factor substitution to show that some local increases in the number of terms may lead to better final synthesis results. Besides, the behavior of depth-first search (DFS) and breadth-first search (BFS) synthesis algorithms are investigated. It is demonstrated that BFS has more effects on the quality of results and sometimes leads to shorter runtime. Based on these properties, a new hybrid DFS/BFS synthesis algorithm is proposed. Our experiments show the efficiency of this algorithm
BibTeX: @inproceedings{2007_Saeedi, author = {Saeedi, M. and Zamani, M.S. and Sedighi, M.}, title = {On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement}, journal = {VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on}, year = {2007}, pages = {428 -436}, doi = {http://dx.doi.org/10.1109/ISVLSI.2007.72} }
Saeedi, M.; Sedighi, M. & Zamani, M.	A novel synthesis algorithm for reversible circuits [Abstract] [BibTeX]	2007	Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on , pp. 65 -68	inproceedings	DOI
Abstract: In this paper, a new non-search based synthesis algorithm for reversible circuits is proposed. Compared with the widely used search-based methods, our algorithm is guaranteed to produce a result and can lead to a solution with much fewer steps. To evaluate the proposed method, several circuits taken from the literature are used. The experimental results corroborate the expected findings.
BibTeX: @inproceedings{2007_Saeedia, author = {Saeedi, M. and Sedighi, M. and Zamani, M.S.}, title = {A novel synthesis algorithm for reversible circuits}, journal = {Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on}, year = {2007}, pages = {65 -68}, doi = {http://dx.doi.org/10.1109/ICCAD.2007.4397245} }
Tu, D.; Shang, L.; Liu, M.; Wang, C.; Jiang, G. & Song, Y.	Electrical bistable behavior of an organic thin film through proton transfer [Abstract] [BibTeX]	2007	Applied Physics Letters Vol. 90 (5) , pp. 052111 -052111-3	article	DOI
Abstract: This letter reports the synthesis of an organic molecule N,N #x2032;-bis (salicylidene)-1,6-hexanaphthenediamine (BSH) and the study of its electrical properties. Reversible electrical bistable behavior was observed both in BSH organic thin film on indium tin oxide substrate and in a crossbar device fabricated via standard integrated circuit processing with this thin film. The proton transfer model, induced by a bias higher than the switch threshold voltage, was employed to explain the electrical bistable phenomenon. This electrical bistability of BSH molecules is a key property for potential applications in organic nonvolatile memories and programable switches.
BibTeX: @article{2007_Tu, author = {Tu, Deyu and Shang, Liwei and Liu, Ming and Wang, Congshun and Jiang, Guiyuan and Song, Yanlin}, title = {Electrical bistable behavior of an organic thin film through proton transfer}, journal = {Applied Physics Letters}, year = {2007}, volume = {90}, number = {5}, pages = {052111 -052111-3}, doi = {http://dx.doi.org/10.1063/1.2431461} }
Wille, R. & Grosse, D.	Fast exact toffoli network synthesis of reversible logic [Abstract] [BibTeX]	2007	Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on , pp. 60 -64	inproceedings	DOI
Abstract: The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of generalized Toffoli networks are considered. We present an improvement of an existing synthesis approach that is based on Boolean Satisfiability. Furthermore, the principle limits of the original and the improved approach are shown. Then, we propose a new method using problem specific knowledge during the synthesis process to overcome these limits. Experimental results demonstrate improvements of the overall synthesis time up to four orders of magnitude.
BibTeX: @inproceedings{2007_Wille, author = {Wille, R. and Grosse, D.}, title = {Fast exact toffoli network synthesis of reversible logic}, journal = {Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on}, year = {2007}, pages = {60 -64}, doi = {http://dx.doi.org/10.1109/ICCAD.2007.4397244} }
Wu, C.; Zhu, X.; Wang, C.; Sheng, H.; Yang, J. & Xie, Y.	Bamboolike carbon nitride nanotubes (C9N5H3): Atomic-scale construction, synthesis and lithium battery applications [Abstract] [BibTeX]	2007	Applied Physics Letters Vol. 90 (11) , pp. 113116 -113116-3	article	DOI
Abstract: The authors constructed the finite cluster model of bamboolike carbon nitride nanotubes taking the C9N5H3 as an example. As desired, the C9N5H3 bamboolike nanotubes were prepared in a facile solvent-free system. Both x-ray photoelectron microscopy and elemental analysis give its formula of C9N5H3, while the UV-vis and Fourier transform infrared results agree well with the theoretical predictions. Due to the existence of pore structure in this carbon nitride tube wall, the lithium battery experimental results exhibit a much higher irreversible and reversible capacity than that of the theoretical capacity of graphite (372 nbsp;mA nbsp;h nbsp;g-1).
BibTeX: @article{2007_Wu, author = {Wu, Changzheng and Zhu, Xi and Wang, Chengle and Sheng, Hua and Yang, Jinlong and Xie, Yi}, title = {Bamboolike carbon nitride nanotubes (C9N5H3): Atomic-scale construction, synthesis and lithium battery applications}, journal = {Applied Physics Letters}, year = {2007}, volume = {90}, number = {11}, pages = {113116 -113116-3}, doi = {http://dx.doi.org/10.1063/1.2713227} }
Yang, G.; Song, X.; Perkowski, M.; Hung, W.; Biamonte, J. & Tang, Z.	Four-level realisation of 3-qubit reversible functions [Abstract] [BibTeX]	2007	Computers Digital Techniques, IET Vol. 1 (4) , pp. 382 -388	article	DOI
Abstract: Two questions have been addressed here: how many logic levels are necessary to synthesise a specific instance of a reversible circuit, and how much better to have large gate libraries, and what gates should be required in libraries. Group theory is applied to 3-bit reversible gate synthesis to create a library useful in hierarchical design. It has been shown that arbitrary 3-bit reversible circuit can be synthesised with four-logic levels, using this new gate library. The respective universal library for the four-level synthesis is constructed and optimised it on the level of nuclear magnetic resonance pulses. A very fast algorithm to synthesise arbitrary 3-bit reversible function to gates from our library is also presented. The algorithm demonstrates dramatic speed benefit and results in a maximum of four-level circuit for arbitrary 3-bit reversible function. The gates are optimised on the level of pulses to decrease their cost and allow for objective comparison with standard CNOT, NOT, Toffoli gates (CNT) circuits. This library guarantees a four-level circuit for any 3-qubit reversible function and is also intended to be used in a hierarchical design of larger circuits.
BibTeX: @article{2007_Yang, author = {Yang, G. and Song, X. and Perkowski, M.A. and Hung, W.N.N. and Biamonte, J. and Tang, Z.}, title = {Four-level realisation of 3-qubit reversible functions}, journal = {Computers Digital Techniques, IET}, year = {2007}, volume = {1}, number = {4}, pages = {382 -388}, doi = {http://dx.doi.org/10.1049/iet-cdt:20060097} }
Zhong, J. & Muzio, J.	Improved Implementation of a Reed-Muller Spectra Based Reversible Synthesis Algorithm [Abstract] [BibTeX]	2007	Communications, Computers and Signal Processing, 2007. PacRim 2007. IEEE Pacific Rim Conference on , pp. 202 -205	inproceedings	DOI
Abstract: Reversible logic synthesis has been gaining much attention recently. There are many synthesis approaches including those using spectral techniques. In this paper, we discuss an improved implementation of a reversible synthesis algorithm for Toffoli networks based on Reed-Muller spectra. We use a compact RM spectral table in the algorithm to reduce runtime and memory occupation. This method is proved to be able to speed up synthesis for many benchmark reversible functions.
BibTeX: @inproceedings{2007_Zhong, author = {Jing Zhong and Muzio, J.C.}, title = {Improved Implementation of a Reed-Muller Spectra Based Reversible Synthesis Algorithm}, journal = {Communications, Computers and Signal Processing, 2007. PacRim 2007. IEEE Pacific Rim Conference on}, year = {2007}, pages = {202 -205}, doi = {http://dx.doi.org/10.1109/PACRIM.2007.4313211} }
Zilic, Z.; Radecka, K. & Kazamiphur, A.	Reversible Circuit Technology Mapping from Non-reversible Specifications [Abstract] [BibTeX]	2007	Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07 , pp. 1 -6	inproceedings	DOI
Abstract: This paper considers the synthesis of reversible circuits directly from an irreversible specification, with no need for producing a reversible embedding first. The authors present a feasible methodology for realizing the networks of reversible gates, in a manner that builds on the classical technology mapping. We do not restrict ourselves to the restricted notion of realizing permutation functions, and construct reversible implementations where extraneous signals are efficiently reused for overcoming the inherent fanout limitation
BibTeX: @inproceedings{2007_Zilic, author = {Zilic, Z. and Radecka, K. and Kazamiphur, A.}, title = {Reversible Circuit Technology Mapping from Non-reversible Specifications}, journal = {Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07}, year = {2007}, pages = {1 -6}, doi = {http://dx.doi.org/10.1109/DATE.2007.364652} }
GroBe, D.; Chen, X. & Drechsler, R.	Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability [Abstract] [BibTeX]	2006	Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on , pp. 51 -54	inproceedings	DOI
Abstract: Compact synthesis result for reversible logic is of major interest in low-power design and quantum computing. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean satisfiability (SAT) instances. Such an instance is satisfiable iff there exists a network representation with d gates. Thus we can guarantee minimality. For a set of benchmarks experimental results are given
BibTeX: @inproceedings{2006_GroBe, author = {Daniel GroBe and Xiaobo Chen and Rolf Drechsler}, title = {Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability}, journal = {Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on}, year = {2006}, pages = {51 -54}, doi = {http://dx.doi.org/10.1109/DCAS.2006.321031} }
Guan, Z.; Qin, X.; Ge, Z. & Zhang, Y.	Reversible Synthesis with Minimum logic function [Abstract] [BibTeX]	2006	Computational Intelligence and Security, 2006 International Conference on Vol. 2 , pp. 968 -971	inproceedings	DOI
Abstract: A first practical logic function reversible synthesis method has been presented. In this method, minimizing a standard logic function for obtained a SOP of optimization in our approach previously. This efficient conversion between SOP and fixed polarity Reed-Muller (FPRM) forms. The results show that the algorithm is efficient in terms of time and space. We also proposed the synthesis algorithm for reversible functions. It uses fixed polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. Some examples of NCMC benchmarks with a large number of variables were presented to demonstrate the suitability of the algorithm for synthesizing complex functions
BibTeX: @inproceedings{2006_Guan, author = {Zhijin Guan and Xiaolin Qin and Ziming Ge and Yiqing Zhang}, title = {Reversible Synthesis with Minimum logic function}, journal = {Computational Intelligence and Security, 2006 International Conference on}, year = {2006}, volume = {2}, pages = {968 -971}, doi = {http://dx.doi.org/10.1109/ICCIAS.2006.295405} }
Gupta, P.; Agrawal, A. & Jha, N.	An Algorithm for Synthesis of Reversible Logic Circuits [Abstract] [BibTeX]	2006	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 25 (11) , pp. 2317 -2330	article	DOI
Abstract: Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25
BibTeX: @article{2006_Gupta, author = {Gupta, P. and Agrawal, A. and Jha, N.K.}, title = {An Algorithm for Synthesis of Reversible Logic Circuits}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2006}, volume = {25}, number = {11}, pages = {2317 -2330}, doi = {http://dx.doi.org/10.1109/TCAD.2006.871622} }
Hu, J.; Ma, G. & Feng, G.	Efficient Algorithm for Positive-polarity Reed-muller Expansions of reversible circuits [Abstract] [BibTeX]	2006	Microelectronics, 2006. ICM '06. International Conference on , pp. 63 -66	inproceedings	DOI
Abstract: In this paper, we build mathematical modeling for reversible circuits and derive required parameters of cost function from this modeling. The heuristic algorithm plots out reversible circuit into some partitions, uses a priority queue based on search tree and explores candidate components at each partition in order of utilization ratio. We demonstrate that using this heuristic, path delay can be reduced by 8% compared to existing synthesis method. The improvements increase for strict delay constraints making synthesis especially important for high performance and a large number of inputs and outputs designs.
BibTeX: @inproceedings{2006_Hu, author = {Jing Hu and GuangSheng Ma and Gang Feng}, title = {Efficient Algorithm for Positive-polarity Reed-muller Expansions of reversible circuits}, journal = {Microelectronics, 2006. ICM '06. International Conference on}, year = {2006}, pages = {63 -66}, doi = {http://dx.doi.org/10.1109/ICM.2006.373267} }
Hung, W.; Song, X.; Yang, G.; Yang, J. & Perkowski, M.	Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis [Abstract] [BibTeX]	2006	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 25 (9) , pp. 1652 -1663	article	DOI
Abstract: This paper proposes an approach to optimally synthesize quantum circuits by symbolic reachability analysis, where the primary inputs and outputs are basis binary and the internal signals can be nonbinary in a multiple-valued domain. The authors present an optimal synthesis method to minimize quantum cost and some speedup methods with nonoptimal quantum cost. The methods here are applicable to small reversible functions. Unlike previous works that use permutative reversible gates, a lower level library that includes nonpermutative quantum gates is used here. The proposed approach obtains the minimum cost quantum circuits for Miller gate, half adder, and full adder, which are better than previous results. This cost is minimum for any circuit using the set of quantum gates in this paper, where the control qubit of 2-qubit gates is always basis binary. In addition, the minimum quantum cost in the same manner for Fredkin, Peres, and Toffoli gates is proven. The method can also find the best conversion from an irreversible function to a reversible circuit as a byproduct of the generality of its formulation, thus synthesizing in principle arbitrary multi-output Boolean functions with quantum gate library. This paper constitutes the first successful experience of applying formal methods and satisfiability to quantum logic synthesis
BibTeX: @article{2006_Hung, author = {Hung, W.N.N. and Xiaoyu Song and Guowu Yang and Jin Yang and Perkowski, M.}, title = {Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2006}, volume = {25}, number = {9}, pages = {1652 -1663}, doi = {http://dx.doi.org/10.1109/TCAD.2005.858352} }
Lee, S.-H.; Ko, D.-K.; Jung, Y. & Agarwal, R.	Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires [Abstract] [BibTeX]	2006	Applied Physics Letters Vol. 89 (22) , pp. 223116 -223116-3	article	DOI
Abstract: Synthesis and device characteristics of highly scalable GeTe nanowire-based phase transition memory are reported. The authors have demonstrated reversible phase transition memory switching behavior in GeTe nanowires, and obtained critical device parameters, such as write and erase currents, threshold voltage, and programming curves. The diameter dependence of memory switching behavior in GeTe nanowires was studied and a systematic reduction of writing currents with decreasing diameter was observed, with currents as low as 0.42 nbsp;mA for a 28 nbsp;nm nanowire. Results show that nanowires are very promising for scalable memory applications and for studying size-dependent phase transition mechanisms at the nanoscale.
BibTeX: @article{2006_Lee, author = {Lee, Se-Ho and Ko, Dong-Kyun and Jung, Yeonwoong and Agarwal, Ritesh}, title = {Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires}, journal = {Applied Physics Letters}, year = {2006}, volume = {89}, number = {22}, pages = {223116 -223116-3}, doi = {http://dx.doi.org/10.1063/1.2397558} }
Ma, X.; Huang, J.; Metra, C. & Lombardi, F.	Testing Reversible 1D Arrays for Molecular QCA [Abstract] [BibTeX]	2006	Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on , pp. 71 -79	inproceedings	DOI
Abstract: Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. As the bijective nature of reversibility makes testing significantly easier than in the general case, testing of the reversible gates is pursued in detail. C-testability of a 1D array is investigated for single cell fault as well multiple cell faults. Defect analysis of the reversible gates is pursued under a single missing/additional cell assumption
BibTeX: @inproceedings{2006_Ma, author = {Ma, X. and Huang, J. and Metra, C. and Lombardi, F.}, title = {Testing Reversible 1D Arrays for Molecular QCA}, journal = {Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on}, year = {2006}, pages = {71 -79}, doi = {http://dx.doi.org/10.1109/DFT.2006.63} }
Maslov, D.	Efficient reversible and quantum implementations of symmetric Boolean functions [Abstract] [BibTeX]	2006	Circuits, Devices and Systems, IEE Proceedings - Vol. 153 (5) , pp. 467 -472	article	DOI
Abstract: It is a well-known fact in logic design that synthesis of some special classes of Boolean functions is often easier than the synthesis of a general unrestricted specification. In reversible logic, well-scaled synthesis methods with a reasonably small cost of the associated implementation have been found for only a few classes of functions. This includes synthesis of multiple-output symmetric and reversible linear functions. The author presents an efficient reversible/quantum synthesis method for the class of multiple-output symmetric functions. The method is purely theoretical, therefore its scaling on functions with a large number of inputs/outputs requires minimal resources. The author calculates garbage, i.e. the number of outputs that are not required by the function specification, the number of reversible gates, and the quantum cost of the presented implementations. The proposed approach is then applied to the synthesis of benchmark functions. Comparison of the designs to the previously reported implementations is favourable
BibTeX: @article{2006_Maslov, author = {Maslov, D.}, title = {Efficient reversible and quantum implementations of symmetric Boolean functions}, journal = {Circuits, Devices and Systems, IEE Proceedings -}, year = {2006}, volume = {153}, number = {5}, pages = {467 -472}, doi = {http://dx.doi.org/10.1049/ip-cds:20045213} }
Miller, D.; Thornton, M. & Goodman, D.	A Decision Diagram Package for Reversible and Quantum Circuit Simulation [Abstract] [BibTeX]	2006	Evolutionary Computation, 2006. CEC 2006. IEEE Congress on , pp. 2428 -2435	inproceedings	DOI
Abstract: This paper presents a decision diagram structure intended for the simulation and verification of reversible and quantum circuits. The structure is designed to efficiently represent the matrices describing reversible and quantum gate and circuit behaviour and takes advantage of key properties of those matrices. Algorithms are described for efficiently building the decision diagram representation directly from a gate without constructing the actual matrix and for performing matrix multiplication which is the fundamental operation to determine the function realized by a cascade of gates. Experimental results show the methods presented are applicable to large circuits at the state of the art in reversible and quantum synthesis and design.
BibTeX: @inproceedings{2006_Miller, author = {Miller, D.M. and Thornton, M.A. and Goodman, D.}, title = {A Decision Diagram Package for Reversible and Quantum Circuit Simulation}, journal = {Evolutionary Computation, 2006. CEC 2006. IEEE Congress on}, year = {2006}, pages = {2428 -2435}, doi = {http://dx.doi.org/10.1109/CEC.2006.1688610} }
Parhami, B.	Fault-Tolerant Reversible Circuits [Abstract] [BibTeX]	2006	Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on , pp. 1726 -1729	inproceedings	DOI
Abstract: Reversible hardware computation, that is, performing logic signal transformations in a way that allows the original input signals to be recovered from the produced outputs, is helpful in diverse areas such as quantum computing, low-power design, nanotechnology, optical information processing, and bioinformatics. We propose a paradigm for performing such reversible computations in a manner that renders a wide class of circuit faults readily detectable at the circuit's outputs. More specifically, we introduce a class of reversible logic gates (consisting of the well-known Fredkin gate and a newly defined Feynman double-gate) for which the parity of the outputs matches that of the inputs. Such parity-preserving reversible gates, when used with an arbitrary synthesis strategy for reversible logic circuits, allow any fault that affects no more than a single logic signal to be detectable at the circuit's primary outputs. We show the applicability of our design strategy by demonstrating how the well-known, and very useful, Toffoli gate can be synthesized from parity- preserving gates and apply the results to the design of a binary full-adder circuit, which is a versatile and widely used element in digital arithmetic processing.
BibTeX: @inproceedings{2006_Parhami, author = {Parhami, B.}, title = {Fault-Tolerant Reversible Circuits}, journal = {Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on}, year = {2006}, pages = {1726 -1729}, doi = {http://dx.doi.org/10.1109/ACSSC.2006.355056} }
Van Rentergem, Y.; De Vos, A. & De Keyser, K.	Using group theory in reversible computing [Abstract] [BibTeX]	2006	Evolutionary Computation, 2006. CEC 2006. IEEE Congress on , pp. 2397 -2404	inproceedings	DOI
Abstract: The (2w)! reversible transformations on w wires, i.e. reversible logic circuits with w inputs and w outputs, together with the action of cascading, form a group, isomorphic to the symmetric group S2w. Therefore, we investigate the group Sn as well as one of its subgroups isomorphic to Sn/2 times Sn/2. We then consider the left cosets, the right cosets, and the double cosets generated by the subgroup. Each element of a coset can function as the representative of the coset. Different choices of the coset space and different choices of the coset representatives lead to four different syntheses for implementing an arbitrary reversible logic operation into hardware. Comparison leads to a best choice: a single coset space, with representatives that are generalized TOFFOLI and FREDKIN gates.
BibTeX: @inproceedings{2006_VanRentergem, author = {Van Rentergem, Y. and De Vos, A. and De Keyser, K.}, title = {Using group theory in reversible computing}, journal = {Evolutionary Computation, 2006. CEC 2006. IEEE Congress on}, year = {2006}, pages = {2397 -2404}, doi = {http://dx.doi.org/10.1109/CEC.2006.1688605} }
Yang, G.; Xie, F.; Song, X.; Hung, W. & Perkowski, M.	A Constructive Algorithm for Reversible Logic Synthesis [Abstract] [BibTeX]	2006	Evolutionary Computation, 2006. CEC 2006. IEEE Congress on , pp. 2416 -2421	inproceedings	DOI
Abstract: This paper presents a constructive synthesis algorithm for any n-qubit reversible function. Given any n-qubit reversible function, there are N distinct input patterns different from their corresponding outputs, where N les 2n, and the other (2n - N) input patterns will be the same as their outputs. We show that this circuit can be synthesized by at most 2nldrN '(n - 1)'-CNOT gates and 4n2 ldr N NOT gates. The time complexity of our algorithm has asymptotic upper bound O(n ldr 4n). The space complexity of our synthesis algorithm is also O(n ldr 2n). The computational complexity of our synthesis algorithm is exponentially lower than the complexity of breadth-first search based synthesis algorithm.
BibTeX: @inproceedings{2006_Yang, author = {Guowu Yang and Fei Xie and Xiaoyu Song and Hung, W.N.N. and Perkowski, M.A.}, title = {A Constructive Algorithm for Reversible Logic Synthesis}, journal = {Evolutionary Computation, 2006. CEC 2006. IEEE Congress on}, year = {2006}, pages = {2416 -2421}, doi = {http://dx.doi.org/10.1109/CEC.2006.1688608} }
Yuan, D.; BaiYan; WenTao, L. & Yi, G.	Research and implementation of reversible logic synthesis algorithmin digital system [Abstract] [BibTeX]	2006	Computer-Aided Industrial Design and Conceptual Design, 2006. CAIDCD '06. 7th International Conference on , pp. 1 -7	inproceedings	DOI
Abstract: The reversible logic synthesis is one of the important methods in the digital system's fault testing and investigating area. As the designing and manufacturing technique of vary large scale digital systems fast develops, under current computer conditions, how to rapidly and accurately implement the reversible logic synthesis of a vary large scale digital systems is a knotty problem that the computer aided logic design researchers have been difficult to resolve and can not evade. Based on deeply studying logical synthesis theories, this paper presented an algorithm called iterative intersection of subset, improved reversible logic synthesis algorithm, and made efficiency experiments of the algorithm. The outcome showed that the reversible logic synthesis performance of vary large scale digital systems using iterative intersection algorithm is markedly superior to the traditional logical synthesis algorithm
BibTeX: @inproceedings{2006_Yuan, author = {Ding Yuan and BaiYan and Lu WenTao and Guo Yi}, title = {Research and implementation of reversible logic synthesis algorithmin digital system}, journal = {Computer-Aided Industrial Design and Conceptual Design, 2006. CAIDCD '06. 7th International Conference on}, year = {2006}, pages = {1 -7}, doi = {http://dx.doi.org/10.1109/CAIDCD.2006.329380} }
Zhong, J. & Muzio, J.	Using Crosspoint Faults in Simplifying Toffoli Networks [Abstract] [BibTeX]	2006	Circuits and Systems, 2006 IEEE North-East Workshop on , pp. 129 -132	inproceedings	DOI
Abstract: Reversible logic computing is a rapidly developing research area. The synthesis of reversible logic and finding minimum-cost circuits are very important issues in this area. In this paper, the authors introduce a new method to detect redundancy in a reversible circuit and, by deleting redundant portions; the authors can simplify the circuit. This approach is based on a new fault model, the crosspoint fault, for reversible logic circuits. The authors show that multiple crosspoint faults are useful in synthesizing reversible circuits implemented with Toffoli networks. Experimental results from benchmark circuits show that some of the circuits can be simplified by deleting all pairs of independent multiple crosspoint faults, with the resulting circuit being functionally equivalent to the original
BibTeX: @inproceedings{2006_Zhong, author = {Jing Zhong and Muzio, J.C.}, title = {Using Crosspoint Faults in Simplifying Toffoli Networks}, journal = {Circuits and Systems, 2006 IEEE North-East Workshop on}, year = {2006}, pages = {129 -132}, doi = {http://dx.doi.org/10.1109/NEWCAS.2006.250942} }
Chakraborty, A.	Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays [Abstract] [BibTeX]	2005	VLSI Design, 2005. 18th International Conference on , pp. 249 - 254	inproceedings	DOI
Abstract: Reversibility is of interest in the design of very low-power circuits; it is essential for quantum computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at fault model (both single stuck-at fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets TUTS such that each C(n) has a unique test set T(n) in TUTS that detects all F-type faults in every member of C(n). We show that if k ge; 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n2 + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model; this number is determined by the size of the RILA cell's state table.
BibTeX: @inproceedings{2005_Chakraborty, author = {Chakraborty, A.}, title = {Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays}, journal = {VLSI Design, 2005. 18th International Conference on}, year = {2005}, pages = { 249 - 254}, doi = {http://dx.doi.org/10.1109/ICVD.2005.158} }
Maslov, D.; Young, C.; Miller, D. & Dueck, G.	Quantum circuit simplification using templates [Abstract] [BibTeX]	2005	Design, Automation and Test in Europe, 2005. Proceedings , pp. 1208 - 1213 Vol. 2	inproceedings	DOI
Abstract: Optimal synthesis of quantum circuits is intractable and heuristic methods must be employed. Templates are a general approach to reversible quantum circuit simplification. We consider the use of templates to simplify a quantum circuit initially found by other means. We present and analyze templates in the general case, and then provide particular details for circuits composed of NOT, CNOT and controlled-sqrt-of-NOT gates. We introduce templates for this set of gates and apply them to simplify both known quantum realizations of Toffoli gates and circuits found by earlier heuristic Fredkin and Toffoli gate synthesis algorithms. While the number of templates is quite small, the reduction in quantum cost is often significant.
BibTeX: @inproceedings{2005_Maslov, author = {Maslov, D. and Young, C. and Miller, D.M. and Dueck, G.W.}, title = {Quantum circuit simplification using templates}, journal = {Design, Automation and Test in Europe, 2005. Proceedings}, year = {2005}, pages = { 1208 - 1213 Vol. 2}, doi = {http://dx.doi.org/10.1109/DATE.2005.249} }
Maslov, D.; Miller, D. & Dueck, G.	Templates for reversible circuit simplification [Abstract] [BibTeX]	2005	Communications, Computers and signal Processing, 2005. PACRIM. 2005 IEEE Pacific Rim Conference on , pp. 609 - 612	inproceedings	DOI
Abstract: Even using quite powerful computers, it is still only feasible to find guaranteed optimal circuits for at most 3-input 3-output reversible Boolean functions. Hence, a number of heuristic synthesis methods have emerged. Application of such methods usually results in non-optimal circuit specifications, which can, potentially, be simplified. The template approach discussed in this paper is a local optimization technique for reversible circuit simplification that can be applied for general cost metrics. We present some results on the efficient construction, generalized classification, and completeness of a set of generalized Toffoli gate templates.
BibTeX: @inproceedings{2005_Maslova, author = {Maslov, D. and Miller, D.M. and Dueck, G.W.}, title = {Templates for reversible circuit simplification}, journal = {Communications, Computers and signal Processing, 2005. PACRIM. 2005 IEEE Pacific Rim Conference on}, year = {2005}, pages = { 609 - 612}, doi = {http://dx.doi.org/10.1109/PACRIM.2005.1517363} }
Maslov, D.; Dueck, G. & Miller, D.	Synthesis of Fredkin-Toffoli reversible networks [Abstract] [BibTeX]	2005	Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Vol. 13 (6) , pp. 765 - 769	article	DOI
Abstract: Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate and the Fredkin gate. We present a method that synthesizes a network with these gates in two steps. First, our synthesis algorithm finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead. Next we apply transformations that reduce the number of gates in the network. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence of gates in the network to be reduced matches a sequence of gates comprising more than half of a template, then a transformation that reduces the gate count can be applied. We have synthesized all three input, three output reversible functions and here compare our results to the optimal results. We also present the results of applying our synthesis tool to obtain networks for a number of benchmark functions.
BibTeX: @article{2005_Maslovb, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Synthesis of Fredkin-Toffoli reversible networks}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, year = {2005}, volume = {13}, number = {6}, pages = { 765 - 769}, doi = {http://dx.doi.org/10.1109/TVLSI.2005.844284} }
Maslov, D.; Dueck, G. & Miller, D.	Toffoli network synthesis with templates [Abstract] [BibTeX]	2005	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 24 (6) , pp. 807 - 817	article	DOI
Abstract: Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired function. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the above synthesis approach. We present a basic method and, based on that, a bidirectional synthesis algorithm which produces a network of Toffoli gates realizing a given reversible specification. An asymptotically optimal modification of the basic synthesis algorithm employing generalized mEXOR gates is also presented. Transformations are then applied using template matching. The basis for a template is a network of gates that realizes the identity function. If a sequence of gates in the synthesized network matches a sequence comprised of more than half the gates in a template, then a transformation using the remaining gates in the template can be applied resulting in a reduction in the gate count for the synthesized network. All templates with up to six gates are described in this paper. Experimental results including an exhaustive examination of all 3-variable reversible functions and a collection of benchmark problems are presented. The paper concludes with suggestions for further research.
BibTeX: @article{2005_Maslovc, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Toffoli network synthesis with templates}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2005}, volume = {24}, number = {6}, pages = { 807 - 817}, doi = {http://dx.doi.org/10.1109/TCAD.2005.847911} }
Thapliyal, H. & Srinivas, M.	Novel design and reversible logic synthesis of multiplexer based full adder and multipliers [Abstract] [BibTeX]	2005	Circuits and Systems, 2005. 48th Midwest Symposium on , pp. 1593 - 1596 Vol. 2	inproceedings	DOI
Abstract: Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3 times;3 reversible gate termed TKS gate having two of its outputs working as 2:1 multiplexer. The proposed TKS gate is used to design a reversible half adder and is further used to design multiplexer based reversible full adder. The multiplexer based full adder is further used to design reversible 4 times;4 Array and modified Baugh Wooley multipliers. A novel 4 times;4 multiplier architecture with reversible logic is also proposed in which the partial products can be generated in parallel and their additions are reduced to logarithmic steps. In the proposed multiplier, all the operations are decomposed into levels, thereby significantly reducing the power consumption through a control circuitry which will switch off those levels which are not active. Thus, this work provides the initial threshold to building of complex systems which can execute more complicated operations. The reversible circuits designed and proposed in this paper form the basis for an ALU of a primitive quantum CPU.
BibTeX: @inproceedings{2005_Thapliyal, author = {Thapliyal, H. and Srinivas, M.B.}, title = {Novel design and reversible logic synthesis of multiplexer based full adder and multipliers}, journal = {Circuits and Systems, 2005. 48th Midwest Symposium on}, year = {2005}, pages = { 1593 - 1596 Vol. 2}, doi = {http://dx.doi.org/10.1109/MWSCAS.2005.1594420} }
Yang, G.; Song, X.; Hung, W. & Perkowski, M.	Bi-direction synthesis for reversible circuits [Abstract] [BibTeX]	2005	VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on , pp. 14 - 19	inproceedings	DOI
Abstract: Quantum computing is one of the most promising emerging technologies of the future. Reversible circuits are an important class of quantum circuits. In this paper, we investigate the problem of optimally synthesizing four-qubit reversible circuits. We present an enhanced bidirectional synthesis approach. Due to the super-exponential increase on the memory requirement, all the existing methods can only perform four steps for the CNP (Control-Not gate, NOT gate, and Peres gate) library. Our novel method can achieve 12 steps. As a result, we augment the number of circuits that can be optimally synthesized by over 5*106 times. Moreover, our approach is faster than the existing approaches by orders of magnitude. The promising experimental results demonstrate the effectiveness of our approach.
BibTeX: @inproceedings{2005_Yang, author = {Guowu Yang and Xiaoyu Song and Hung, W.N.N. and Perkowski, M.A.}, title = {Bi-direction synthesis for reversible circuits}, journal = {VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on}, year = {2005}, pages = { 14 - 19}, doi = {http://dx.doi.org/10.1109/ISVLSI.2005.21} }
Yang, G.; Song, X.; Hung, W. & Perkowski, M.	Fast synthesis of exact minimal reversible circuits using group theory [Abstract] [BibTeX]	2005	Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific Vol. 2 , pp. 1002 - 1005 Vol. 2	inproceedings	DOI
Abstract: We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory problems, we use the powerful algebraic software GAP to solve such problems. Our algorithms are not only able to minimize for arbitrary cost functions of gates, but also orders of magnitude faster than the existing approaches to reversible logic synthesis. In addition, we show that the Peres gate is a better choice than the standard Toffoli gate in libraries of universal reversible gates.
BibTeX: @inproceedings{2005_Yanga, author = {Guowu Yang and Xiaoyu Song and Hung, W.N.N. and Perkowski, M.A.}, title = {Fast synthesis of exact minimal reversible circuits using group theory}, journal = {Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific}, year = {2005}, volume = {2}, pages = { 1002 - 1005 Vol. 2}, doi = {http://dx.doi.org/10.1109/ASPDAC.2005.1466509} }
Yang, G.; Hung, W.; Song, X. & Perkowski, M.	Exact synthesis of 3-qubit quantum circuits from non-binary quantum gates using multiple-valued logic and group theory [Abstract] [BibTeX]	2005	Design, Automation and Test in Europe, 2005. Proceedings , pp. 434 - 435 Vol. 1	inproceedings	DOI
Abstract: We propose an approach to optimally synthesize quantum circuits from non-permutative quantum gates such as controlled-square-root-of-not (i.e., controlled-V). Our approach reduces the synthesis problem to multiple-valued optimization and uses group theory. We devise a novel technique that transforms the quantum logic synthesis problem from a multi-valued constrained optimization problem to a group permutation problem. The transformation enables us to utilize group theory to exploit the properties of the synthesis problem. Assuming a cost of one for each two-qubit gate, we find all reversible circuits with quantum costs of 4, 5, 6, etc, and give another algorithm to realize these reversible circuits with quantum gates.
BibTeX: @inproceedings{2005_Yangb, author = {Guowu Yang and Hung, W.N.N. and Xiaoyu Song and Perkowski, M.}, title = {Exact synthesis of 3-qubit quantum circuits from non-binary quantum gates using multiple-valued logic and group theory}, journal = {Design, Automation and Test in Europe, 2005. Proceedings}, year = {2005}, pages = { 434 - 435 Vol. 1}, doi = {http://dx.doi.org/10.1109/DATE.2005.145} }
Agrawal, A. & Jha, N.	Synthesis of reversible logic [Abstract] [BibTeX]	2004	Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Vol. 2 , pp. 1384 - 1385 Vol.2	inproceedings	DOI
Abstract: A function is reversible if each input vector produces a unique output vector. Reversible functions find applications in low power design, quantum computing, and nanotechnology. Logic synthesis for reversible circuits differs substantially from traditional logic synthesis. In this paper, we present the first practical synthesis algorithm and tool for reversible functions with a large number of inputs. It uses positive-polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. The heuristic uses a priority queue based search tree and explores candidate factors at each stage in order of attractiveness. The algorithm produces near-optimal results for the examples discussed in the literature. The key contribution of the work is that the heuristic finds very good solutions for reversible functions with a large number of inputs.
BibTeX: @inproceedings{2004_Agrawal, author = {Agrawal, A. and Jha, N.K.}, title = {Synthesis of reversible logic}, journal = {Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings}, year = {2004}, volume = {2}, pages = { 1384 - 1385 Vol.2}, doi = {http://dx.doi.org/10.1109/DATE.2004.1269099} }
Al-Rabadi, A.	Quantum circuit synthesis using classes of GF(3) reversible fast spectral transforms [Abstract] [BibTeX]	2004	Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on , pp. 87 - 93	inproceedings	DOI
Abstract: Novel quantum circuit synthesis, using reversible Davio expansions, is introduced. The new method uses two planes to synthesize the quantum circuits: (1) a reversible butterfly circuit plane; and (2) a plane of quantum gates to perform additions and multiplications. Since the reduction of power consumption is a major requirement for circuit design of future technologies, such as in quantum circuits, the main features of several future technologies must include reversibility, and thus the new synthesis method, using reversible butterfly circuits, can play an important role in the synthesis of circuits that consume minimal power.
BibTeX: @inproceedings{2004_Al-Rabadi, author = {Al-Rabadi, A.N.}, title = {Quantum circuit synthesis using classes of GF(3) reversible fast spectral transforms}, journal = {Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on}, year = {2004}, pages = { 87 - 93}, doi = {http://dx.doi.org/10.1109/ISMVL.2004.1319925} }
Al-Rabadi, A.	Reversible fast permutation transforms for quantum circuit synthesis [Abstract] [BibTeX]	2004	Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on , pp. 81 - 86	inproceedings	DOI
Abstract: Multiple-valued quantum circuit synthesis, using permutation-based fast transforms, is introduced. Since the reduction of power consumption is a major requirement for circuit design in future technologies, such as in quantum computing, the main features of several future technologies must include reversibility. Consequently, the new quantum circuits can play an important task in the design of future circuits that consume minimal power.
BibTeX: @inproceedings{2004_Al-Rabadia, author = {Al-Rabadi, A.N.}, title = {Reversible fast permutation transforms for quantum circuit synthesis}, journal = {Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on}, year = {2004}, pages = { 81 - 86}, doi = {http://dx.doi.org/10.1109/ISMVL.2004.1319924} }
Babu, H.; Islam, M.; Chowdhury, S. & Chowdhury, A.	Synthesis of full-adder circuit using reversible logic [Abstract] [BibTeX]	2004	VLSI Design, 2004. Proceedings. 17th International Conference on , pp. 757 - 760	inproceedings	DOI
Abstract: A reversible gate has the equal number of inputs and outputs and one-to-one mappings between input vectors and output vectors; so that, the input vector states can be always uniquely reconstructed from the output vector states. This correspondence introduces a reversible full-adder circuit that requires only three reversible gates and produces least number of "garbage outputs ", that is two. After that, a theorem has been proposed that proves the optimality of the propounded circuit in terms of number of garbage outputs. An efficient algorithm is also introduced in this paper that leads to construct a reversible circuit.
BibTeX: @inproceedings{2004_Babu, author = {Babu, H.M.H. and Islam, M.R. and Chowdhury, S.M.A. and Chowdhury, A.R.}, title = {Synthesis of full-adder circuit using reversible logic}, journal = {VLSI Design, 2004. Proceedings. 17th International Conference on}, year = {2004}, pages = { 757 - 760}, doi = {http://dx.doi.org/10.1109/ICVD.2004.1261020} }
de Garis, H. & Batty, T.	The evolution of robust, reversible, nano-scale, femtosecond-switching circuits [Abstract] [BibTeX]	2004	Evolvable Hardware, 2004. Proceedings. 2004 NASA/DoD Conference on , pp. 291 - 297	inproceedings	DOI
Abstract: This paper introduces conceptual problems that will arise in the next 10-20 years as electronic circuits reach nanometer scale, i.e. the size of molecules. Suc1.09"h circuits will be impossible to make perfectly, due to the inevitable fabrication faults in chips with an Avogadro number of components. Hence they will need to be constructed so that they are robust to faults. They will also need to be (as far as possible) reversible circuits, to avoid the heat dissipation problem if bits of information are routinely wiped out during the computational process. They will also have to be local if the switching times reach femtoseconds, which is possible now with quantum optics. This paper discusses some of the conceptual issues involved in trying to build circuits that satisfy all these criteria, i.e. that they are robust, reversible and local. We propose an evolutionary engineering based model that meets all these criteria, and provide some experimental results to justify it.
BibTeX: @inproceedings{2004_Garis, author = {de Garis, H. and Batty, T.}, title = {The evolution of robust, reversible, nano-scale, femtosecond-switching circuits}, journal = {Evolvable Hardware, 2004. Proceedings. 2004 NASA/DoD Conference on}, year = {2004}, pages = { 291 - 297}, doi = {http://dx.doi.org/10.1109/EH.2004.1310843} }
Jayawickrama, Y. & Rajakaruna, S.	Ultracapacitor based ride-through system for a DC load [Abstract] [BibTeX]	2004	Power System Technology, 2004. PowerCon 2004. 2004 International Conference on Vol. 1 , pp. 232 - 237 Vol.1	inproceedings	DOI
Abstract: Ultracapacitor is an emerging energy storage device suitable for high-power, short-term applications. In this paper, a ride-through system for a DC load based on the ultracapacitors and a current-reversible buck-boost converter is analyzed. Compared to an equivalent battery operated converter in the boost mode with continuous inductor current, the control to output transfer function of the ultracapacitor-based converter has an additional right half plane zero located very close to the origin. As a result, the achievable bandwidth of the controller is very low and a steady-state error prevails in the load voltage if the controller is designed to operate in the stable mode. However, if zero steady-state error in the load voltage is desired, it can be achieved by operating the system with some degree of instability during the short period of disturbance.
BibTeX: @inproceedings{2004_Jayawickrama, author = {Jayawickrama, Y.R.L. and Rajakaruna, S.}, title = {Ultracapacitor based ride-through system for a DC load}, journal = {Power System Technology, 2004. PowerCon 2004. 2004 International Conference on}, year = {2004}, volume = {1}, pages = { 232 - 237 Vol.1}, doi = {http://dx.doi.org/10.1109/ICPST.2004.1459998} }
Kerntopf, P.	A new heuristic algorithm for reversible logic synthesis [BibTeX]	2004	Design Automation Conference, 2004. Proceedings. 41st , pp. 834 - 837	inproceedings
BibTeX: @inproceedings{2004_Kerntopf, author = {Kerntopf, P.}, title = {A new heuristic algorithm for reversible logic synthesis}, journal = {Design Automation Conference, 2004. Proceedings. 41st}, year = {2004}, pages = { 834 - 837} }
Maslov, D. & Dueck, G.	Reversible cascades with minimal garbage [Abstract] [BibTeX]	2004	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 23 (11) , pp. 1497 - 1509	article	DOI
Abstract: The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. We start with the analysis of the number of garbage outputs that must be added to a multiple output function to make it reversible. We give a precise formula for the theoretical minimum of the required number of garbage outputs. For some benchmark functions, we calculate the garbage required by some proposed reversible design methods and compare it to the theoretical minimum. Based on the information about minimal garbage, we suggest a new reversible design method that uses the minimum number of garbage outputs. We show that any Boolean function can be realized as a reversible network in terms of this new approach by giving the theoretical method of finding such a network. Using a heuristics synthesis approach, we create a program and run it to compare results of our synthesis to the previously reported synthesis results for the benchmark functions with up to ten variables. Finally, we show that the synthesis for the proposed model can be accomplished with lower cost than the synthesis of EXOR programmable logic arrays.
BibTeX: @article{2004_Maslov, author = {Maslov, D. and Dueck, G.W.}, title = {Reversible cascades with minimal garbage}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2004}, volume = {23}, number = {11}, pages = { 1497 - 1509}, doi = {http://dx.doi.org/10.1109/TCAD.2004.836735} }
Morgan, M. & Bruce, J.	The CRL gateway [Abstract] [BibTeX]	2004	Potentials, IEEE Vol. 22 (5) , pp. 8 - 11	article	DOI
Abstract: Smaller and smaller semiconductor integrated circuits are being designed. Traditional semiconductor fabrication processes are still extremely effective. However, these methods' effectiveness will come to a halt as components shrink to atomic size. Quantum physics then start to govern device behavior. Thus a radical shift, hence upheaval (change is never easy), in computing is a foregone conclusion. But the resulting quantum computers will be tremendously powerful. As our circuits become smaller, the heat they generate becomes harder to control. Much of this heat is a result of the logic function itself, rather than simple resistive dissipation. Therefore, new forms of logic must be considered. Conservative reversible logic (CRL) can reduce the problem of energy dissipated due to logic functions and can be utilized to build quantum computers. Before that can happen, research must be done on how to utilize these gates. Also, a usable synthesis process must be designed. Unparalleled computing power, power savings, and resources are being uncovered. The paper discusses CRL-based gates. They are only models, but models must exist to meet the technology developments required to build quantum computers.
BibTeX: @article{2004_Morgan, author = { Morgan, M. and Bruce, J.W.}, title = {The CRL gateway}, journal = {Potentials, IEEE}, year = {2004}, volume = {22}, number = {5}, pages = { 8 - 11}, doi = {http://dx.doi.org/10.1109/MP.2004.1301238} }
Wang, Y. & Zhu, S.-C.	Analysis and synthesis of textured motion: particles and waves [Abstract] [BibTeX]	2004	Pattern Analysis and Machine Intelligence, IEEE Transactions on Vol. 26 (10) , pp. 1348 -1363	article	DOI
Abstract: Natural scenes contain a wide range of textured motion phenomena which are characterized by the movement of a large amount of particle and wave elements, such as falling snow, wavy water, and dancing grass. In this paper, we present a generative model for representing these motion patterns and study a Markov chain Monte Carlo algorithm for inferring the generative representation from observed video sequences. Our generative model consists of three components. The first is a photometric model which represents an image as a linear superposition of image bases selected from a generic and overcomplete dictionary. The dictionary contains Gabor and LoG bases for point/particle elements and Fourier bases for wave elements. These bases compete to explain the input images and transfer them to a token (base) representation with an O(102)-fold dimension reduction. The second component is a geometric model which groups spatially adjacent tokens (bases) and their motion trajectories into a number of moving elements-called "motons". A moton is a deformable template in time-space representing a moving element, such as a falling snowflake or a flying bird. The third component is a dynamic model which characterizes the motion of particles, waves, and their interactions. For example, the motion of particle objects floating in a river, such as leaves and balls, should be coupled with the motion of waves. The trajectories of these moving elements are represented by coupled Markov chains. The dynamic model also includes probabilistic representations for the birth/death (source/sink) of the motons. We adopt a stochastic gradient algorithm for learning and inference. Given an input video sequence, the algorithm iterates two steps: 1) computing the motions and their trajectories by a number of reversible Markov chain jumps, and 2) learning the parameters that govern the geometric deformations and motion dynamics. Novel video sequences are synthesized from the learned models and, by editing the model parameters, we demonstrate the controllability of the generative model.
BibTeX: @article{2004_Wang, author = {Yizhou Wang and Song-Chun Zhu}, title = {Analysis and synthesis of textured motion: particles and waves}, journal = {Pattern Analysis and Machine Intelligence, IEEE Transactions on}, year = {2004}, volume = {26}, number = {10}, pages = {1348 -1363}, doi = {http://dx.doi.org/10.1109/TPAMI.2004.76} }
Babu, H.M.H.; Islam, M.R.; Chowdhury, A.R. & Chowdhury, S.M.A.	Reversible logic synthesis for minimization of full-adder circuit [Abstract] [BibTeX]	2003	Digital System Design, 2003. Proceedings. Euromicro Symposium on , pp. 50 - 54	inproceedings	DOI
Abstract: Reversible logic is of the growing importance to many future technologies. A reversible circuit maps each output vector, into a unique input vector, and vice versa. This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the "garbage bit" and number of reversible gates, which is the main challenge of reversible logic synthesis. This proposed full-adder circuit contains only three gates and two garbage outputs whereas earlier full-adder circuit by M. Perkowski et al. (2001) requires four gates and produces two garbage outputs and another existing full-adder circuit by Md. H. H Azad Khan (2002) requires three gates but produces three garbage outputs. Thus, the proposed full-adder circuit is efficient in terms of number of gates with compared to M. Perkowski et al. (2001) as well as in terms of number of garbage outputs with compared to Md. H. H Azad Khan (2002).
BibTeX: @inproceedings{2003_Babu, author = {Hafiz Md Hasan Babu and Md Rafiqul Islam and Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury}, title = {Reversible logic synthesis for minimization of full-adder circuit}, journal = {Digital System Design, 2003. Proceedings. Euromicro Symposium on}, year = {2003}, pages = { 50 - 54}, doi = {http://dx.doi.org/10.1109/DSD.2003.1231899} }
Dueck, G.; Maslov, D. & Miller, D.	Transformation-based synthesis of networks of Toffoli/Fredkin gates [Abstract] [BibTeX]	2003	Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on Vol. 1 , pp. 211 - 214 vol.1	inproceedings
Abstract: Reversible logic has attracted significant attention in recent years. It has applications in low power CMOS, quantum computing, nanotechnology, and optical computing. Traditional gates such as AND, OR, and EXOR are not reversible. In fact NOT is the only reversible gate from the traditional set of gates. Several reversible gates have been proposed. Among them are the controlled NOT (also known as the Feynman gate), the Toffoli gate, and the Fredkin gate. An n-input Toffoli gate has n - 1 control lines which pass through the gate unaltered and a target line on which the value is inverted if all the control lines have value '1'. An n-input Fredkin gate has n - 2 control lines which pass through the gate unaltered and two target lines on which the values are swapped if all the control lines have value '1'. A NOT gate is the special case of a Toffoli gate with no control inputs. Likewise, a SWAP gate is the special case of a Fredkin gate with no control inputs. In this paper, we review a transformation-based synthesis procedure targeted to Toffoli gates and show how it can be extended to allow Fredkin gates. This extension results in circuits with fewer gates. The synthesis of reversible logic differs significantly from traditional irreversible logic synthesis approaches. Fan-outs and loops are not permitted due to the target technology. Outputs from one gate are used as inputs to the next gate. This results in a high degree of interdependence among gates. Our algorithm first finds an initial circuit with no backtracking and minimal look-ahead. We exploit reversibility directly in our synthesis approach. This method always finds a solution. Next we apply a set of template transforms that reduce the size of the circuit. We synthesize all three input, three output reversible functions and compare our results to those obtained previously.
BibTeX: @inproceedings{2003_Dueck, author = {Dueck, G.W. and Maslov, D. and Miller, D.M.}, title = {Transformation-based synthesis of networks of Toffoli/Fredkin gates}, journal = {Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on}, year = {2003}, volume = {1}, pages = { 211 - 214 vol.1} }
Khan, M.; Perkowski, M. & Kerntopf, P.	Multi-output Galois Field Sum of Products synthesis with new quantum cascades [Abstract] [BibTeX]	2003	Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on , pp. 146 - 153	inproceedings	DOI
Abstract: Galois Field Sum of Products (GFSOP) leads to efficient multi-valued reversible circuit synthesis using quantum gates. In this paper, we propose a new generalization of ternary Toffoli gate and another new generalized reversible ternary gale with discussion of their quantum realizations. Algorithms for synthesizing ternary GFSOP using quantum cascades of these gates are proposed In both the synthesis methods, 5 ternary shift operators and ternary swap gate are used We also propose quantum realizations of 5 ternary shift operators and ternary swap gate. In the cascades of the new ternary gates, local mirrors, variable ordering, and product ordering techniques are used to reduce the circuit cost. Experimental results show that the cascade of the new ternary gates is more efficient than the cascade of ternary Toffoli gates.
BibTeX: @inproceedings{2003_Khan, author = {Khan, M.H.A. and Perkowski, M.A. and Kerntopf, P.}, title = {Multi-output Galois Field Sum of Products synthesis with new quantum cascades}, journal = {Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on}, year = {2003}, pages = { 146 - 153}, doi = {http://dx.doi.org/10.1109/ISMVL.2003.1201399} }
Maslov, D.; Dueck, G. & Miller, D.	Fredkin/Toffoli templates for reversible logic synthesis [Abstract] [BibTeX]	2003	Computer Aided Design, 2003. ICCAD-2003. International Conference on , pp. 256 - 261	inproceedings
Abstract: Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate and the Fredkin gate. Our synthesis algorithm first finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead. Next we apply transformations that reduce the size of the circuit. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence in the network to be synthesized matches more than half of a template, then a transformation that reduces the gate count can be applied. In this paper we show that Toffoli and Fredkin gates behave in a similar manner. Therefore, some gates in the templates may not need to be specified-they can match a Toffoli or a Fredkin gate. We formalize this by introducing the box gate. All templates with less than six gates are enumerated and classified. We synthesize all three input, three output reversible functions and compare our results to those obtained previously.
BibTeX: @inproceedings{2003_Maslov, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Fredkin/Toffoli templates for reversible logic synthesis}, journal = {Computer Aided Design, 2003. ICCAD-2003. International Conference on}, year = {2003}, pages = { 256 - 261} }
Maslov, D.; Dueck, G. & Miller, D.	Simplification of Toffoli networks via templates [Abstract] [BibTeX]	2003	Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on , pp. 53 - 58	inproceedings
Abstract: Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired junction. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the second step. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence in the network to be synthesized matches more than half of a template, then a transformation reducing the gate count can be applied. All templates for m le;7 are described in this paper.
BibTeX: @inproceedings{2003_Maslova, author = {Maslov, D. and Dueck, G.W. and Miller, D.M.}, title = {Simplification of Toffoli networks via templates}, journal = {Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on}, year = {2003}, pages = { 53 - 58} }
Maslov, D. & Dueck, G.	Improved quantum cost for n-bit Toffoli gates [Abstract] [BibTeX]	2003	Electronics Letters Vol. 39 (25) , pp. 1790 - 1791	article	DOI
Abstract: An n-bit Toffoli gate quantum circuit based on the
BibTeX: @article{2003_Maslovb, author = {Maslov, D. and Dueck, G.W.}, title = {Improved quantum cost for n-bit Toffoli gates}, journal = {Electronics Letters}, year = {2003}, volume = {39}, number = {25}, pages = { 1790 - 1791}, doi = {http://dx.doi.org/10.1049/el:20031202} }
Miller, D.; Maslov, D. & Dueck, G.	A transformation based algorithm for reversible logic synthesis [Abstract] [BibTeX]	2003	Design Automation Conference, 2003. Proceedings , pp. 318 - 323	inproceedings
Abstract: A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing, nanotechnology and low-power CMOS design. Synthesis approaches are not well developed for reversible circuits even for small numbers of inputs and outputs. In this paper, a transformation based algorithm for the synthesis of such a reversible circuit in terms of n times; n Toffoli gates is presented. Initially, a circuit is constructed by a single pass through the specification with minimal look-ahead and no back-tracking. Reduction rules are then applied by simple template matching. The method produces very good results for larger problems.
BibTeX: @inproceedings{2003_Miller, author = {Miller, D.M. and Maslov, D. and Dueck, G.W.}, title = {A transformation based algorithm for reversible logic synthesis}, journal = {Design Automation Conference, 2003. Proceedings}, year = {2003}, pages = { 318 - 323} }
Shende, V.; Prasad, A.; Markov, I. & Hayes, J.	Synthesis of reversible logic circuits [Abstract] [BibTeX]	2003	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Vol. 22 (6) , pp. 710 - 722	article	DOI
Abstract: Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics, and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). We prove constructively that every even permutation can be implemented without temporary storage using NOT, CNOT, and TOFFOLI gates. We describe an algorithm for the synthesis of optimal circuits and study the reversible functions on three wires, reporting the distribution of circuit sizes. We also study canonical circuit decompositions where gates of the same kind are grouped together. Finally, in an application important to quantum computing, we synthesize oracle circuits for Grover's search algorithm, and show a significant improvement over a previously proposed synthesis algorithm.
BibTeX: @article{2003_Shende, author = {Shende, V.V. and Prasad, A.K. and Markov, I.L. and Hayes, J.P.}, title = {Synthesis of reversible logic circuits}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, year = {2003}, volume = {22}, number = {6}, pages = { 710 - 722}, doi = {http://dx.doi.org/10.1109/TCAD.2003.811448} }
Yashchyshyn, Y.; Synyavskyy, A. & Modelski, J.	Evaluation of possibilities of solving the inverse scattering problem for multilayered structures in the case of plane wave [Abstract] [BibTeX]	2003	CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of , pp. 307 - 310	inproceedings
Abstract: Investigation of approaches to solving of one-dimensional inverse scattering problem of electromagnetic waves is presented in the paper. Two approaches were analysed in detail as alternative ways of inverse scattering problem solving. One of them is based on analytical solution of Riccati equation and other realizes minimization of objective function defined by character of inverse problem. Efficiency of investigated methods was estimated at the solving of both profile reconstruction and multilayered structures synthesis starting from frequency dependence of reflection coefficients.
BibTeX: @inproceedings{2003_Yashchyshyn, author = {Yashchyshyn, Y. and Synyavskyy, A. and Modelski, J.}, title = {Evaluation of possibilities of solving the inverse scattering problem for multilayered structures in the case of plane wave}, journal = {CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of}, year = {2003}, pages = { 307 - 310} }
Zhou, K. & Wang, D.	Digital repetitive controlled three-phase PWM rectifier [Abstract] [BibTeX]	2003	Power Electronics, IEEE Transactions on Vol. 18 (1) , pp. 309 - 316	article	DOI
Abstract: In this paper, a digital repetitive control (RC) strategy is proposed to achieve zero tracking error for constant-voltage constant-frequency (CVCF) pulse width modulation (PWM) converters. The proposed control scheme is of "plug-in" structure: a plug-in digital repetitive controller plus a conventional controller (e.g., PD controller). The design of the plug-in repetitive learning controller is systematically developed. The stability analysis of overall system is discussed. A repetitive controlled three-phase reversible PWM rectifier is given as an application example. Near unity power factor and constant output DC voltage are ensured under parameter uncertainties and load disturbances. Simulation and experimental results are provided to testify the effectiveness of the proposed control scheme.
BibTeX: @article{2003_Zhou, author = {Keliang Zhou and Wang, D.}, title = {Digital repetitive controlled three-phase PWM rectifier}, journal = {Power Electronics, IEEE Transactions on}, year = {2003}, volume = {18}, number = {1}, pages = { 309 - 316}, doi = {http://dx.doi.org/10.1109/TPEL.2002.807150} }
Adams, M. & Ward, R.	Two families of symmetry-preserving reversible integer-to-integer wavelet transforms [Abstract] [BibTeX]	2002	Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on Vol. 2 , pp. II-600 - II-603 vol.2	inproceedings
Abstract: Two families of symmetry-preserving reversible integer-to-integer wavelet transforms are introduced. We explain how transforms from these families can be used in conjunction with symmetric extension in order to handle signals of arbitrary length in a nonexpansive manner (which is often a desirable attribute in signal coding applications). The characteristics of the two transform families and their constituent transforms are then studied. For the more constrained of the two families, we identify precisely which transforms belong to the family (by specifying properties and conditions for membership). Such results might be exploited in the filter bank design process in order to find new symmetry-preserving reversible integer-to-integer wavelet transforms for signal coding applications
BibTeX: @inproceedings{2002_Adams, author = {Adams, M.D. and Ward, R.}, title = {Two families of symmetry-preserving reversible integer-to-integer wavelet transforms}, journal = {Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on}, year = {2002}, volume = {2}, pages = { II-600 - II-603 vol.2} }
Guillorn, M.A.; McKnight, T.E.; Melechko, A.; Merkulov, V.I.; Britt, P.F.; Austin, D.W.; Lowndes, D.H. & Simpson, M.L.	Individually addressable vertically aligned carbon nanofiber-based electrochemical probes [Abstract] [BibTeX]	2002	Journal of Applied Physics Vol. 91 (6) , pp. 3824 -3828	article	DOI
Abstract: In this paper we present the fabrication and initial testing results of high aspect ratio vertically aligned carbon nanofiber (VACNF)-based electrochemical probes. Electron beam lithography was used to define the catalytic growth sites of the VACNFs. Following catalyst deposition, VACNF were grown using a plasma enhanced chemical vapor deposition process. Photolithography was performed to realize interconnect structures. These probes were passivated with a thin layer of SiO2, which was then removed from the tips of the VACNF, rendering them electrochemically active. We have investigated the functionality of completed devices using cyclic voltammetry (CV) of ruthenium hexammine trichloride, a highly reversible, outer sphere redox system. The faradaic current obtained during CV potential sweeps shows clear oxidation and reduction peaks at magnitudes that correspond well with the geometry of these nanoscale electrochemical probes. Due to the size and the site-specific directed synthesis of the VACNFs, these probes are ideally suited for characterizing electrochemical phenomena with an unprecedented degree of spatial resolution. #xa9; 2002 American Institute of Physics.
BibTeX: @article{2002_Guillorn, author = {Guillorn, M. A. and McKnight, T. E. and Melechko, A. and Merkulov, V. I. and Britt, P. F. and Austin, D. W. and Lowndes, D. H. and Simpson, M. L.}, title = {Individually addressable vertically aligned carbon nanofiber-based electrochemical probes}, journal = {Journal of Applied Physics}, year = {2002}, volume = {91}, number = {6}, pages = {3824 -3828}, doi = {http://dx.doi.org/10.1063/1.1448671} }
Kerntopf, P.	Synthesis of multipurpose reversible logic gates [Abstract] [BibTeX]	2002	Digital System Design, 2002. Proceedings. Euromicro Symposium on , pp. 259 - 266	inproceedings	DOI
Abstract: Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose reversible gates are also shown.
BibTeX: @inproceedings{2002_Kerntopf, author = {Kerntopf, P.}, title = {Synthesis of multipurpose reversible logic gates}, journal = {Digital System Design, 2002. Proceedings. Euromicro Symposium on}, year = {2002}, pages = { 259 - 266}, doi = {http://dx.doi.org/10.1109/DSD.2002.1115377} }
Miller, D.	Spectral and two-place decomposition techniques in reversible logic [Abstract] [BibTeX]	2002	Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on Vol. 2 , pp. II-493 - II-496 vol.2	inproceedings
Abstract: A digital circuit is reversible if it maps each input vector into a unique output vector. Reversible circuits can lead to low-power CMOS implementations and are also of interest in optical and quantum computing. In this paper, we consider the synthesis of reversible logic assuming primitive reversible devices such as Feynman, Toffoli and Fredkin gates. In particular, we consider the use of Rademacher-Walsh spectral techniques and two-place decompositions of Boolean functions. Preliminary results are given for reversible and nonreversible functions and show that the approaches described do indeed show promise.
BibTeX: @inproceedings{2002_Miller, author = {Miller, D.M.}, title = {Spectral and two-place decomposition techniques in reversible logic}, journal = {Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on}, year = {2002}, volume = {2}, pages = { II-493 - II-496 vol.2} }
Ohno, H.	Molecular beam epitaxy and properties of ferromagnetic III-V semiconductors [Abstract] [BibTeX]	2002	Molecular Beam Epitaxy, 2002 International Conference on , pp. 9 - 10	inproceedings	DOI
Abstract: Owing to the nonmagnetic nature of III-V compounds magnetic cooperative phenomena were not a part of the rich soil of III-V heterostructures in the past. The synthesis of magnetic III-V semiconductors and subsequent discovery of carrier-induced ferromagnetism in them now allows us to combine ferromagnetism with the properties of III-V heterostructures. Here, I describe molecular beam epitaxy of ferromagnetic III/V's, a mean-field model for the carrier-induced ferromagnetism in them, and isothermal and reversible electric field control of carrier-induced ferromagnetism in a ferromagnetic semiconductor (In,Mn)As.
BibTeX: @inproceedings{2002_Ohno, author = {Ohno, H.}, title = {Molecular beam epitaxy and properties of ferromagnetic III-V semiconductors}, journal = {Molecular Beam Epitaxy, 2002 International Conference on}, year = {2002}, pages = { 9 - 10}, doi = {http://dx.doi.org/10.1109/MBE.2002.1037734} }
Shende, V.; Prasad, A.; Markov, I. & Hayes, J.	Reversible logic circuit synthesis [Abstract] [BibTeX]	2002	Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on , pp. 353 - 360	inproceedings	DOI
Abstract: Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). We prove constructively that every even permutation can be implemented without temporary storage using NOT, CNOT and TOFFOLI gates. We describe an algorithm for the synthesis of optimal circuits and study the reversible functions on three wires, reporting distributions of circuit sizes. Finally, in an application important to quantum computing, we synthesize oracle circuits for Grover's search algorithm, and show a significant improvement over a previously proposed synthesis algorithm.
BibTeX: @inproceedings{2002_Shende, author = {Shende, V.V. and Prasad, A.K. and Markov, I.L. and Hayes, J.P.}, title = {Reversible logic circuit synthesis}, journal = {Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on}, year = {2002}, pages = { 353 - 360}, doi = {http://dx.doi.org/10.1109/ICCAD.2002.1167558} }
Cheylan, S. & Elliman, R.G.	Effect of hydrogen on the photoluminescence of Si nanocrystals embedded in a SiO2 matrix [Abstract] [BibTeX]	2001	Applied Physics Letters Vol. 78 (9) , pp. 1225 -1227	article	DOI
Abstract: Hydrogen passivation of Si nanocrystals is shown to result in a redshift of photoluminescence (PL) emission spectra, as well as the more commonly observed intensity increase. The shift is reversible, with spectra returning to their unpassivated values as hydrogen is removed from the samples by annealing. The magnitude of the redshift also depends on the implant fluence employed for nanocrystal synthesis, increasing with increasing fluence or particle size. These data are shown to be consistent with a model in which larger crystallites are assumed to contain a greater number of nonradiative defects, i.e., the number of nonradiative defects is assumed to scale with the surface area or volume of a nanocrystal. Hydrogen passivation then results in a disproportionate increase in emission from larger crystallites, giving rise to an apparent redshift in the composite PL emission spectrum. #xa9; 2001 American Institute of Physics.
BibTeX: @article{2001_Cheylan, author = {Cheylan, S. and Elliman, R. G.}, title = {Effect of hydrogen on the photoluminescence of Si nanocrystals embedded in a SiO2 matrix}, journal = {Applied Physics Letters}, year = {2001}, volume = {78}, number = {9}, pages = {1225 -1227}, doi = {http://dx.doi.org/10.1063/1.1338492} }
Perkowski, M.; Kerntopf, P.; Buller, A.; Chrzanowska-Jeske, M.; Mishchenko, A.; Song, X.; Al-Rabadi, A.; Jezwiak, L.; Coppola, A. & Massey, B.	Regular realization of symmetric functions using reversible logic [Abstract] [BibTeX]	2001	Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on , pp. 245 -252	inproceedings	DOI
Abstract: Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2*2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little ldquo;garbage rdquo;. Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can also be used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs
BibTeX: @inproceedings{2001_Perkowski, author = {Perkowski, M. and Kerntopf, P. and Buller, A. and Chrzanowska-Jeske, M. and Mishchenko, A. and Xiaoyu Song and Al-Rabadi, A. and Jezwiak, L. and Coppola, A. and Massey, B.}, title = {Regular realization of symmetric functions using reversible logic }, journal = {Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on}, year = {2001}, pages = {245 -252}, doi = {http://dx.doi.org/10.1109/DSD.2001.952289} }
Yali, X.; Zhengchun, J. & Qiang, X.	Fast dynamic response 3-phase voltage source reversible rectifier for spindle drive [Abstract] [BibTeX]	2001	Electrical Machines and Systems, 2001. ICEMS 2001. Proceedings of the Fifth International Conference on Vol. 1 , pp. 557 -560 vol.1	inproceedings	DOI
Abstract: In this paper, the authors present a control method for a fast dynamic response three-phase voltage source reversible rectifier. Simulation and experiments all show the significant advantages of this method
BibTeX: @inproceedings{2001_Yali, author = {Xiong Yali and Jia Zhengchun and Xu Qiang}, title = {Fast dynamic response 3-phase voltage source reversible rectifier for spindle drive}, journal = {Electrical Machines and Systems, 2001. ICEMS 2001. Proceedings of the Fifth International Conference on}, year = {2001}, volume = {1}, pages = {557 -560 vol.1}, doi = {http://dx.doi.org/10.1109/ICEMS.2001.970735} }
Bortishevsky, V.; Kashkovsky, V.; Novikova, I.; Zagorodny, V.; Launets, V. & Oliynik, V.	The use of microwave energy for obtaining dry silica sol [Abstract] [BibTeX]	2000	Microwave Conference, 2000. Microwave and Telecommunication Technology. 2000 10th International Crimean , pp. 570 - 571	inproceedings	DOI
Abstract: Presented in this work is an original technique of obtaining high-concentration silica sols which are widely used in various branches of industry. This technique consists of three stages: synthesis, stabilization and drying of the silica sols. Microwave evaporation was used at the stage of final drying and removed the local hot spots of the drying substance, thus helping to avoid the formation of a non-reversible gel. The silica sol was dehydrated till 60% concentration and then placed in the chamber of a teflon reactor. The experiment was carried out at one of the industrial frequencies. The uninterrupted mode of generation was used. Silica sol obtained in this way is 100% reversible, e.g. its dry powder disperses in water to a 100% extent, forming an initial colloidal solution.
BibTeX: @inproceedings{2000_Bortishevsky, author = {Bortishevsky, V.A. and Kashkovsky, V.I. and Novikova, I.A. and Zagorodny, V.V. and Launets, V.L. and Oliynik, V.V.}, title = {The use of microwave energy for obtaining dry silica sol}, journal = {Microwave Conference, 2000. Microwave and Telecommunication Technology. 2000 10th International Crimean}, year = {2000}, pages = { 570 - 571}, doi = {http://dx.doi.org/10.1109/CRMICO.2000.1256231} }
Gupta, A.	Novel multidimensional dynamic super high speed communication in functional media [Abstract] [BibTeX]	2000	Southeastcon 2000. Proceedings of the IEEE , pp. 485 -488	inproceedings	DOI
Abstract: This paper analyzes a super high speed communication system, consisting of multidimensional white noise transmission through novel multidimensional optimal GAMMA media and reversible (unlimited and limited) receiver. It is shown that, in order to achieve variable limit speed, a chemical transmission theory is needed to unify various concepts of chaotic, propagation, optimal and differential equations based media synthesis. It is further shown that data synthesis techniques are applicable to media synthesis and vice versa in variable limit communication feasibility
BibTeX: @inproceedings{2000_Gupta, author = {Gupta, A.K.}, title = {Novel multidimensional dynamic super high speed communication in functional media}, journal = {Southeastcon 2000. Proceedings of the IEEE}, year = {2000}, pages = {485 -488}, doi = {http://dx.doi.org/10.1109/SECON.2000.845617} }
Lee, M.; Weidner, R. & Lu, W.	Mission lifecycle modeling and simulation [Abstract] [BibTeX]	2000	Aerospace Conference Proceedings, 2000 IEEE Vol. 4 , pp. 379 -388 vol.4	inproceedings	DOI
Abstract: Mission synthesis and simulation research at JPL addresses mission model taxonomy, progressive lifecycle representation, model-based design, and simulation-in-the-loop design. The Virtual Mission (VM) project integrates the research activities and implements a virtual mission lifecycle to enable a globally optimal mission. The VM is composed of three interacting modeling and simulation layers: a mission model architecture layer, a mission system simulation layer, and a mission operation simulation layer. The three layers collectively simulate the development, integration, and operation phases of the mission cycle for comprehensive validation of mission design products. The VM was applied for the MICAS (Miniature Imaging Camera And Spectrometer) payload system of the Deep Space 1 mission (DS1) to validate the integrated system's performance to ensure the desired science return. The VM is being applied to design and to validate calibration scenarios and science observation scenarios for the extended science mission of the DS1 project
BibTeX: @inproceedings{2000_Lee, author = {Meemong Lee and Weidner, R.J. and Wenwen Lu}, title = {Mission lifecycle modeling and simulation}, journal = {Aerospace Conference Proceedings, 2000 IEEE}, year = {2000}, volume = {4}, pages = {379 -388 vol.4}, doi = {http://dx.doi.org/10.1109/AERO.2000.878450} }
Wu, W.; Zheng, Y.; Wang, L. & Sun, X.	A novel indirect current controlled realization for the three phase voltage source reversible converter [Abstract] [BibTeX]	2000	Power Electronics and Motion Control Conference, 2000. Proceedings. IPEMC 2000. The Third International Vol. 2 , pp. 985 -989 vol.2	inproceedings	DOI
Abstract: In this paper, the output characteristic of the 3-phase voltage source converter based on a new mathematical model is studied. A practical indirect current realization of the system is carried out, the closed loop regulator is designed and the regulator parameter is configured. To obtain unity power factor, a new algorithm is presented. System experiment results are provided to prove the correctness of the theoretical analysis and the simulation
BibTeX: @inproceedings{2000_Wu, author = {Weiyang Wu and Yingnan Zheng and Liqiao Wang and Xiaofeng Sun}, title = {A novel indirect current controlled realization for the three phase voltage source reversible converter}, journal = {Power Electronics and Motion Control Conference, 2000. Proceedings. IPEMC 2000. The Third International}, year = {2000}, volume = {2}, pages = {985 -989 vol.2}, doi = {http://dx.doi.org/10.1109/IPEMC.2000.884649} }
Zhou, K.; Wang, D. & Xu, G.	Repetitive controlled three-phase reversible PWM rectifier [Abstract] [BibTeX]	2000	American Control Conference, 2000. Proceedings of the 2000 Vol. 1 (6) , pp. 125 -129 vol.1	inproceedings	DOI
Abstract: In this paper, a repetitive current control scheme for three-phase reversible PWM rectifier is proposed. The proposed control scheme is of typical dual-loop structure: inner AC current loop with plug-in repetitive plus feedback deadbeat controller, and outer DC voltage loop with PI controller. The unit power factor and constant DC bus voltage are obtained under load disturbance. Simulation results are illustrated to show the validity of the proposed control scheme
BibTeX: @inproceedings{2000_Zhou, author = {Keliang Zhou and Danwei Wang and Guangyan Xu}, title = {Repetitive controlled three-phase reversible PWM rectifier}, journal = {American Control Conference, 2000. Proceedings of the 2000}, year = {2000}, volume = {1}, number = {6}, pages = {125 -129 vol.1}, doi = {http://dx.doi.org/10.1109/ACC.2000.878786} }
Coiling, I. & Barbi, I.	A reversible step-up voltage-source inverter controlled by sliding mode [Abstract] [BibTeX]	1999	Power Electronics Specialists Conference, 1999. PESC 99. 30th Annual IEEE Vol. 1 , pp. 538 -543 vol.1	inproceedings	DOI
Abstract: The step-up inverter with controlled output current manages DC-to-AC power transfer, with any ratio between the DC and the AC levels. By reversing the energy flow, this circuit becomes a high power factor step-down (or step-up) rectifier. Sliding mode is applied to control the fifth-order system. Simulation results of a 1 kW inverter/rectifier are included to confirm the analysis
BibTeX: @inproceedings{1999_Coiling, author = {Coiling, I.E. and Barbi, I.}, title = {A reversible step-up voltage-source inverter controlled by sliding mode}, journal = {Power Electronics Specialists Conference, 1999. PESC 99. 30th Annual IEEE}, year = {1999}, volume = {1}, pages = {538 -543 vol.1}, doi = {http://dx.doi.org/10.1109/PESC.1999.789067} }
Escobar, G.; Ortega, R. & van der Schaft, A.	A saturated output feedback controller for the three phase voltage sourced reversible boost type rectifier [Abstract] [BibTeX]	1998	Industrial Electronics Society, 1998. IECON '98. Proceedings of the 24th Annual Conference of the IEEE Vol. 2 , pp. 685 -690 vol.2	inproceedings	DOI
Abstract: In this article, the authors present a saturating controller to regulate the output voltage load in a three-phase boost type rectifier. The controller only needs the output voltage signal to be implemented. Moreover, by forcing the inductance currents to track desired suitable sinusoidal signals in phase with the input source voltages, the controller can ensure near unity power factor functioning of the system. The saturation feature in this controller is motivated by the fact that the allowed combinations of switches in the rectifier circuit define a finite set of allowed control vectors, moreover, the convex combinations of these vectors raise up a convex hull in the space of control inputs, a hexagon in this example. Thus, based upon the assumption of fast switching, one can ensure that any control vector lying inside this hexagon, and much more, inside its inscrit circle, can be physically implementable by means of a PWM strategy or a convex combination of the allowed control vectors
BibTeX: @inproceedings{1998_Escobar, author = {Escobar, G. and Ortega, R. and van der Schaft, A.J.}, title = {A saturated output feedback controller for the three phase voltage sourced reversible boost type rectifier}, journal = {Industrial Electronics Society, 1998. IECON '98. Proceedings of the 24th Annual Conference of the IEEE}, year = {1998}, volume = {2}, pages = {685 -690 vol.2}, doi = {http://dx.doi.org/10.1109/IECON.1998.724176} }
Verdelho, P. & Marques, G.	DC voltage control and stability analysis of PWM-voltage-type reversible rectifiers [Abstract] [BibTeX]	1998	Industrial Electronics, IEEE Transactions on Vol. 45 (2) , pp. 263 -273	article	DOI
Abstract: A PWM voltage rectifier has useful characteristics on its DC and AC sides. On its DC side, a DC-link unidirectional voltage is obtained and bidirectional power transfer capability is possible by reversing the flow direction of the DC-link current. On its AC side, near sinusoidal current waveforms and AC four-quadrant operation can be obtained, leading to high-quality power being exchanged between the power converter and the mains. The use of AC filters becomes unnecessary. The rectifier DC voltage must be regulated to a constant value. In this paper, three solutions for the DC voltage control are presented. In the first solution, the DC voltage is controlled by acting upon the quadrature component of the power converter fundamental Park's voltages with relation to the mains voltages. Slow responses are necessary because of stability reasons. Also, load power variations produce both active and reactive power variations in the power converter AC side. To improve the DC voltage response, a second control solution is presented. The power converter currents in Park's coordinates must be controlled. The DC voltage is controlled by controlling the direct Park's current component and, thus, acting only on the active power of the converter AC side. Faster responses are achieved. In this case, load power variations do not produce reactive power variations in the converter AC side. The third control solution is a simplified version of this last one. Experimental results from a 2 kVA IGBT-based prototype showing good system dynamic performance are presented
BibTeX: @article{1998_Verdelho, author = {Verdelho, P. and Marques, G.D.}, title = {DC voltage control and stability analysis of PWM-voltage-type reversible rectifiers}, journal = {Industrial Electronics, IEEE Transactions on}, year = {1998}, volume = {45}, number = {2}, pages = {263 -273}, doi = {http://dx.doi.org/10.1109/41.681225} }
Fraser, M. & Manning, C.	True average current predictive controller for four-wire PWM reversible rectifiers [Abstract] [BibTeX]	1997	Electric Power Applications, IEE Proceedings - Vol. 144 (6) , pp. 397 -400	article
Abstract: A proposed predictive controller suitable for four-wire boost rectifiers is described. The predictive controller regulates the rectifier line currents and includes a method of providing true average current mode control. The performance of the rectifier is demonstrated using simulation results for an 80 kVA rated converter switching at 15 kHz. Practical requirements for the controller are discussed
BibTeX: @article{1997_Fraser, author = {Fraser, M.E. and Manning, C.D.}, title = {True average current predictive controller for four-wire PWM reversible rectifiers}, journal = {Electric Power Applications, IEE Proceedings -}, year = {1997}, volume = {144}, number = {6}, pages = {397 -400} }
Gusev, S.; Johnson, W. & Miller, J.	Active flywheel control based on the method of moment restrictions [Abstract] [BibTeX]	1997	American Control Conference, 1997. Proceedings of the 1997 Vol. 5 , pp. 3426 -3430 vol.5	inproceedings	DOI
Abstract: The paper considers the use of reversible alternator for reducing the engine speed oscillation. The reversible alternator is supposed to replace the flywheel that is normally used for this purpose and we refer to this new device as an active flywheel. The key element of the active flywheel project is the design of alternator controller for speed oscillation damping. The source of the speed oscillation of the engine crankshaft is the periodical combustion process which produces the oscillating torque. We propose the method of moment restriction for the controller synthesis. This robust control method makes it possible to utilize more complete available information on the disturbance spectrum. The numerical realization of the moment restriction method is developed, which is focused on the implementation in the problem considered. The simulation of the active flywheel shows that the moment regulator constructed can reduce the oscillation significantly better than the standard flywheel
BibTeX: @inproceedings{1997_Gusev, author = {Gusev, S.V. and Johnson, W. and Miller, J.}, title = {Active flywheel control based on the method of moment restrictions }, journal = {American Control Conference, 1997. Proceedings of the 1997}, year = {1997}, volume = {5}, pages = {3426 -3430 vol.5}, doi = {http://dx.doi.org/10.1109/ACC.1997.612101} }
Cai, W.; Tan, M.; Wang, G. & Zhang, L.	Reversible transition between transparency and opacity for the porous silica host dispersed with silver nanometer particles within its pores [Abstract] [BibTeX]	1996	Applied Physics Letters Vol. 69 (20) , pp. 2980 -2982	article	DOI
Abstract: The porous silica dispersed with silver nanometer particles (about 3 nm) within its pores (cages) has been prepared by a new method. In the process of alternative exposure to the ambient air and annealing, this material assumes reversible transition between transparency and opacity. This can be explained by oxidation of the outer part of the Ag particles during exposure to the ambient air and dissociation of the oxide during annealing in air. #xa9; 1996 American Institute of Physics.
BibTeX: @article{1996_Cai, author = {Cai, Weiping and Tan, Ming and Wang, Guozhong and Zhang, Lide}, title = {Reversible transition between transparency and opacity for the porous silica host dispersed with silver nanometer particles within its pores}, journal = {Applied Physics Letters}, year = {1996}, volume = {69}, number = {20}, pages = {2980 -2982}, doi = {http://dx.doi.org/10.1063/1.117750} }
Min, K.S.; Shcheglov, K.V.; Yang, C.M.; Atwater, H.A.; Brongersma, M.L. & Polman, A.	The role of quantum hash x2010;confined excitons vs defects in the visible luminescence of SiO2 films containing Ge nanocrystals [Abstract] [BibTeX]	1996	Applied Physics Letters Vol. 68 (18) , pp. 2511 -2513	article	DOI
Abstract: Synthesis of Ge nanocrystals in SiO2 films is carried out by precipitation from a supersaturated solid solution of Ge in SiO2 made by Ge ion implantation. The films exhibit strong room #x2010;temperature visible photoluminescence. The measured photoluminescence peak energy and lifetimes show poor correlations with nanocrystal size compared to calculations involving radiative recombination of quantum #x2010;confined excitons in Ge quantum dots. In addition, the photoluminescence spectra and lifetime measurements show only a weak temperature dependence. These observations strongly suggest that the observed visible luminescence in our samples is not due to the radiative recombination of quantum #x2010;confined excitons in Ge nanocrystals. Instead, observations of similar luminescence in Xe+ #x2010;implanted samples and reversible PL quenching by hydrogen or deuterium suggest that radiative defect centers in the SiO2 matrix are responsible for the observed luminescence. #xa9; 1996 American Institute of Physics.
BibTeX: @article{1996_Min, author = {Min, K. S. and Shcheglov, K. V. and Yang, C. M. and Atwater, Harry A. and Brongersma, M. L. and Polman, A.}, title = {The role of quantum hash x2010;confined excitons vs defects in the visible luminescence of SiO2 films containing Ge nanocrystals}, journal = {Applied Physics Letters}, year = {1996}, volume = {68}, number = {18}, pages = {2511 -2513}, doi = {http://dx.doi.org/10.1063/1.115838} }
Kawai, T.; Koshido, T. & Yoshino, K.	Optical and dielectric properties of photochromic dye in amorphous state and its application [Abstract] [BibTeX]	1995	Applied Physics Letters Vol. 67 (6) , pp. 795 -797	article	DOI
Abstract: Preparation of amorphous phase of a photochromic dye, cis #x2010;1,2 #x2010;dicyano #x2010;1,2 #x2010; bis(2,4,5 #x2010;trimethyl #x2010; 3 #x2010;thienyl) ethene, has been investigated and its photochromic properties have been studied. This photochromic dye shows clear photochromism in the amorphous solid state accompanying reversible changes in absorption spectrum, refractive index, and dielectric properties. Clear optical pattern formation has been achieved on the amorphous dye layer. #xa9; 1995 American Institute of Physics.
BibTeX: @article{1995_Kawai, author = {Kawai, Tsuyoshi and Koshido, Takashi and Yoshino, Katsumi}, title = {Optical and dielectric properties of photochromic dye in amorphous state and its application}, journal = {Applied Physics Letters}, year = {1995}, volume = {67}, number = {6}, pages = {795 -797}, doi = {http://dx.doi.org/10.1063/1.115470} }
Pan, C.-T. & Jiang, M.-C.	Control and implementation of a three-phase voltage-doubler reversible AC to DC converter [Abstract] [BibTeX]	1995	Power Electronics Specialists Conference, 1995. PESC '95 Record., 26th Annual IEEE Vol. 1 , pp. 437 -443 vol.1	inproceedings	DOI
Abstract: In this paper, a novel three-phase bidirectional interface is proposed by using only four active switches to simplify the hardware circuit and achieve unity power factor, sinusoidal input current, adjustable output voltage and bidirectional power flow capability. To ensure obtaining clean input current waveform, the current tracking mechanism is analyzed together with graphical aid and some critical design conditions are presented. Finally, a small-signal model is derived and, in addition to the feedback control, an instantaneous voltage detector is proposed for the added feedforward control to achieve almost zero output impedance and zero audio susceptibility. A prototype hardware circuit is constructed and some experimental results are presented for demonstration
BibTeX: @inproceedings{1995_Pan, author = {Ching-Tsai Pan and Maoh-Chin Jiang}, title = {Control and implementation of a three-phase voltage-doubler reversible AC to DC converter}, journal = {Power Electronics Specialists Conference, 1995. PESC '95 Record., 26th Annual IEEE}, year = {1995}, volume = {1}, pages = {437 -443 vol.1}, doi = {http://dx.doi.org/10.1109/PESC.1995.474847} }
Chaffai, R. & Al-Haddad, K.	Two-quadrant reversible resonance convertor [Abstract] [BibTeX]	1994	Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on , pp. 38 -41 vol.1	inproceedings	DOI
Abstract: The authors aim to determine the structure of a complex convertor in as systematic a manner as possible. This procedure is described in the context of two-quadrant reversible resonance DC-DC convertors with natural switching, with the objective of deducing the structures of convertors able to supply a load of unknown power factor. After presentation of the various topologies arising from this synthesis, and an exposition of the principles of control of such structures, a method of graphical analytic study of these convertors is implemented which enables the operating characteristics to be determined
BibTeX: @inproceedings{1994_Chaffai, author = {Chaffai, R. and Al-Haddad, K.}, title = {Two-quadrant reversible resonance convertor}, journal = {Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on}, year = {1994}, pages = {38 -41 vol.1}, doi = {http://dx.doi.org/10.1109/CCECE.1994.405666} }
Meng, H.; Seneff, S. & Zue, V.	Phonological parsing for reversible letter-to-sound/sound-to-letter generation [Abstract] [BibTeX]	1994	Acoustics, Speech, and Signal Processing, 1994. ICASSP-94., 1994 IEEE International Conference on Vol. ii , pp. II/1 -II/4 vol.2	inproceedings	DOI
Abstract: In this paper, we describe a reversible letter-to-sound/sound-to-letter generation system based on an approach which combines a rule-based formalism with data-driven techniques. We adopt a probabilistic parsing strategy to provide a hierarchical lexical analysis of a word, including information such as morphology, stress, syllabification, phonemics and graphemics. Long-distance constraints are propagated by enforcing local constraints throughout the hierarchy. Our training and testing corpora are derived from the high-frequency portion of the Brown Corpus (10,000 words), augmented with markers indicating stress and word morphology. We evaluated our performance on both letter-to-sound and sound-to-letter generation in terms of whole word accuracy and phoneme/letter accuracy. Using 26 letters and 52 phonemes with an unseen test set, we achieved a word accuracy of 69.3% and a phoneme accuracy of 91.7% for letter-to-sound generation, and a word accuracy of 51.9% and letter accuracy of 88.6% for sound-to-letter generation
BibTeX: @inproceedings{1994_Meng, author = {Meng, H.M. and Seneff, S. and Zue, V.W.}, title = {Phonological parsing for reversible letter-to-sound/sound-to-letter generation}, journal = {Acoustics, Speech, and Signal Processing, 1994. ICASSP-94., 1994 IEEE International Conference on}, year = {1994}, volume = {ii}, pages = {II/1 -II/4 vol.2}, doi = {http://dx.doi.org/10.1109/ICASSP.1994.389733} }
Rubin, L.M.; Orlando, T.P.; Vander Sande, J.B.; Gorman, G.; Savoy, R.; Swope, R. & Beyers, R.	Phase stability limits of Bi2Sr2Ca1Cu2O8+ #x3b4; and Bi2Sr2Ca2Cu3O10+ #x3b4; [Abstract] [BibTeX]	1992	Applied Physics Letters Vol. 61 (16) , pp. 1977 -1979	article	DOI
Abstract: We determined the phase stability limits of Bi2Sr2Ca1Cu2O8+ #x3b4; and Bi2Sr2Ca2Cu3O10+ #x3b4; in the temperature range 650 #x2013;880 #x2009; #xb0;C using a solid #x2010;state electrochemical technique. These phases decompose by incongruent melting above #x223c;790 #x2009; #xb0;C, whereas they decompose by a solid #x2010;state reaction at lower temperatures. The solid #x2010;state decomposition reaction is reversible for Bi2Sr2Ca1Cu2O8+ #x3b4;, but not for Bi2Sr2Ca2Cu3O10+ #x3b4;.
BibTeX: @article{1992_Rubin, author = {Rubin, L. M. and Orlando, T. P. and Vander Sande, J. B. and Gorman, G. and Savoy, R. and Swope, R. and Beyers, R.}, title = {Phase stability limits of Bi2Sr2Ca1Cu2O8+ #x3b4; and Bi2Sr2Ca2Cu3O10+ #x3b4;}, journal = {Applied Physics Letters}, year = {1992}, volume = {61}, number = {16}, pages = {1977 -1979}, doi = {http://dx.doi.org/10.1063/1.108335} }
Currie, A. & Baker, K.	Multiple objective optimisation in behavioural synthesis [Abstract] [BibTeX]	1991	Formal and Semi-Formal Methods for Digital Systems Design, IEE Colloquium on , pp. 5/1 -5/3	inproceedings
Abstract: A behavioural synthesis system named MOODS, is currently under development at the University of Southampton as part of a collaborative project under the auspices of the DTI's Information Engineering Advanced Technology Programme. The overall aim of the project is to produce an efficient implementation in silicon from a behavioural description of a design written in ELLA. The work described in the paper concerns the global optimisation of synthesised control and data paths using reversible design transformations, directed by means of a user-supplied cost function which can incorporate multiple constraints and target objectives
BibTeX: @inproceedings{1991_Currie, author = {Currie, A.J. and Baker, K.R.}, title = {Multiple objective optimisation in behavioural synthesis}, journal = {Formal and Semi-Formal Methods for Digital Systems Design, IEE Colloquium on}, year = {1991}, pages = {5/1 -5/3} }
Moet, A.; Palley, I. & Baer, E.	Development of hard hash x2010;elastic solids from glassy polymers [Abstract] [BibTeX]	1980	Journal of Applied Physics Vol. 51 (10) , pp. 5175 -5183	article	DOI
Abstract: High #x2010;impact polystyrene (HIPS) has been processed into a specific microstructure which exhibited the hard #x2010;elastic behavior previously restricted to crystalline polymers. Unidirectionally stacked profuse crazes formed in uniaxially elongated HIPS resembled the row nucleated structures of stacked lamellar aggregates bridged by extended fibrils. Films in this form possessed repeated high recovery from large extension without rupture. Stress #x2010;strain and stress #x2010;relaxation tests, performed in air and in a variety of liquids, and thermoelastic experiments indicated that this material has similar characteristics to those of hard #x2010;elastic crystalline polymers. Our results confirmed that the recovery process of elastic HIPS, like crystalline systems, is composed of an instantaneous component and a time #x2010;dependent healing mechanism. The first was found to be energetic in nature and the second conformational (entropic). A mechanism, based on the reversible extensive formation of fresh surface of the craze (or interlamellar) fibrils giving rise to the elastic restorative force, is proposed. Stress #x2010;induced sorption and release of liquid, a newly discovered property, is also discussed.
BibTeX: @article{1980_Moet, author = {Moet, Abdelsamie and Palley, Igor and Baer, Eric}, title = {Development of hard hash x2010;elastic solids from glassy polymers}, journal = {Journal of Applied Physics}, year = {1980}, volume = {51}, number = {10}, pages = {5175 -5183}, doi = {http://dx.doi.org/10.1063/1.327421} }
Marcus, S. & Willems, J.	Nonstationary network synthesis via state-space techniques [Abstract] [BibTeX]	1975	Circuits and Systems, IEEE Transactions on Vol. 22 (9) , pp. 713 - 720	article
Abstract: A theory is developed for nonstationary network synthesis via state-space techniques. The method is based on direct realization algorithms from a Hankel matrix (input/output) description of the system. Passive, lossless, reciprocal, reversible, and relaxation systems are considered. For each of these classes of systems, necessary and sufficient conditions on the Hankel matrix for the existence of a representation which can be synthesized with certain types of network elements are derived. In addition, algorithms for computing these representations are presented.
BibTeX: @article{1975_Marcus, author = { Marcus, S. and Willems, J.}, title = {Nonstationary network synthesis via state-space techniques}, journal = {Circuits and Systems, IEEE Transactions on}, year = {1975}, volume = {22}, number = {9}, pages = { 713 - 720} }
Greifer, A.P.	Piezomagnetism of Biased Ferrites [Abstract] [BibTeX]	1964	Journal of Applied Physics Vol. 35 (3) , pp. 1065 -1066	article	DOI
Abstract: New developments in the synthesis and processing of magnetostrictive materials that are highly piezomagnetic in the polarized state are briefly described and interpreted in terms of the relationship for reversible stress sensitivity derived by Bozorth and Williams. In the system MnO #xe5f8;CoO #xe5f8;Fe2O3, a coupling coefficient 0.39 has been obtained for Mn0.970Co0.068Fe1.962O4 and 0.33 for Mn0.932Co0.068Fe2O4. Solid solutions of the nickel cobalt and manganese cobalt ferrites are also piezomagnetic. These materials require atmosphere control during the firing process. When similar processing is applied to the commercially established nickel cobalt ferrites, a coupling coefficient 0.42 is obtained for Ni0.974Co0.026Fe2O4 without requiring quenching from high temperatures. It is suggested that the high piezomagnetic activity of the manganese cobalt ferrites can be understood if the appropriate strain term in the expression derived by Bozorth and Williams is better identified by the easy direction magnetostriction instead of the polycrystalline magnetostriction. This interpretation leads to the prediction that magnetite with the correct cobalt ferrite addition is highly piezomagnetic.
BibTeX: @article{1964_Greifer, author = {Greifer, Aaron P.}, title = {Piezomagnetism of Biased Ferrites}, journal = {Journal of Applied Physics}, year = {1964}, volume = {35}, number = {3}, pages = {1065 -1066}, doi = {http://dx.doi.org/10.1063/1.1713381} }

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